參數(shù)資料
型號： MAX5290AETE
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： DAC
英文描述： Buffered, Fast-Settling, Dual, 12-/10-/8-Bit, Voltage-Output DACs
中文描述： SERIAL INPUT LOADING, 3 us SETTLING TIME, 12-BIT DAC, QCC16
封裝： 4 X 4 MM, 0.80 MM HEIGHT, MO-220WGGC, TQFN-16
文件頁數(shù)： 15/33頁
文件大?。?/td> 941K
代理商： MAX5290AETE
M
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
______________________________________________________________________________________
15
Detailed Description
The MAX5290
–
MAX5295 dual, 12-/10-/8-bit, voltage-
output digital-to-analog converters (DACs) offer
buffered outputs and a 3μs maximum settling time at
the 12-bit level. The DACs operate from a single 2.7V to
3.6V analog supply and a separate 1.8V to AV
DD
digi-
tal supply. The MAX5290
–
MAX5295 include an input
register and DAC register for each channel and a
16-bit data-in/data-out shift register. The 3-wire serial
interface is compatible with SPI, QSPI, MICROWIRE,
and DSP applications. The MAX5290
–
MAX5295 pro-
vide two user-programmable digital I/O ports, which
are programmed through the serial interface. The exter-
nally selectable power-up states of the DAC outputs
are either zero scale, midscale, or full scale.
Reference Input
The reference input, REF, accepts both AC and DC val-
ues with a voltage range extending from 0.25V to
AV
DD
. The voltage at REF (V
REF
) sets the full-scale out-
put of the DACs. Determine the output voltage using
the following equation:
Unity-gain versions:
V
OUT_
= (V
REF
x CODE) / 2
N
Force-sense versions (FB_ connected to OUT_):
V
OUT
= 0.5 x (V
REF
x CODE) / 2
N
where CODE is the numeric value of the DAC
’
s binary
input code and N is the bits of resolution. For the
MAX5290/MAX5291, N = 12 and CODE ranges from 0
to 4095. For the MAX5292/MAX5293, N = 10 and
CODE ranges from 0 to 1023. For the MAX5294/
MAX5295, N = 8 and CODE ranges from 0 to 255.
Output Buffers
The DACA and DACB output-buffer amplifiers of the
MAX5290
–
MAX5295 are unity-gain stable with Rail-to-
Rail
output voltage swings and a typical slew rate of
5.7V/μs. The MAX5290/MAX5292/MAX5294 provide
unity-gain outputs, while the MAX5291/MAX5293/
MAX5295 provide force-sense outputs. For the
MAX5291/MAX5293/MAX5295, access to the output
amplifier
’
s inverting input provides flexibility in output gain
setting and signal conditioning (see the
Applications
Information
section).
The MAX5290
–
MAX5295 offer FAST and SLOW-settling
time modes. In the FAST mode, the settling time is 3μs
(max), and the supply current is 2mA (max). In the SLOW
mode, the settling time is 6μs (max), and the supply cur-
rent drops to 0.8mA (max). See the
Digital Interface
sec-
tion for settling-time mode programming details.
Use the serial interface to set the shutdown output
impedance of the amplifiers to 1k
or 100k
for the
MAX5290/MAX5292/MAX5294 and 1k
or high imped-
ance for the MAX5291/MAX5293/MAX5295. The DAC
outputs can drive a 2k
(typ) load and are stable with
up to 500pF (typ) of capacitive load.
Power-On Reset
At power-up, all DAC outputs power up to full scale,
midscale, or zero scale, depending on the configuration
of the PU input. Connect PU to DV
DD
to set OUT_ to full
scale upon power-up. Connect PU to DGND to set
OUT_ to zero scale upon power-up. Leave PU floating
to set OUT_ to midscale.
Digital Interface
The MAX5290
–
MAX5295 use a 3-wire serial interface
that is compatible with SPI, QSPI, MICROWIRE, and
DSPs (Figures 1 and 2). Connect
DSP
to DV
DD
before
power-up to clock data in on the rising edge of SCLK.
Connect
DSP
to DGND before power-up to clock data in
on the falling edge of SCLK. After power-up, the device
enters DSP frame sync mode on the first rising edge of
DSP
. Refer to the
Programmer’s Handbook
for details.
Each MAX5290
–
MAX5295 includes a 16-bit input shift
register. The data is loaded into the input shift register
through the serial interface. The 16 bits can be sent in
two serial 8-bit packets or one 16-bit word (
CS
must
remain low until all 16 bits are transferred). The data is
loaded MSB first. For the MAX5290/MAX5291, the 16
bits consist of 4 control bits (C3
–
C0) and 12 data bits
(D11
–
D0) (see Table 1). For the 10-bit MAX5292/
MAX5293 devices, D11
–
D2 are the data bits and D1
and D0 are sub-bits. For the 8-bit MAX5294/
MAX5295 devices, D11
–
D4 are the data bits and
D3
–
D0 are sub-bits. Set all sub-bits to zero for optimum
performance.
Each DAC channel includes two registers: an input reg-
ister and the DAC register. At power-up, the DAC out-
put is set according to the state of PU. The DACs are
double-buffered, which allows any of the following for
each channel:
Loading the input register without updating the DAC
register
Loading the DAC register without updating the input
register
Updating the DAC register from the input register
Updating the input and DAC registers simultaneously
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
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