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參數(shù)資料
| 型號(hào)： | MAX527AEWG |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | DAC |
| 英文描述： | 12-Bit Digital-to-Analog Converter |
| 中文描述： | QUAD, PARALLEL, WORD INPUT LOADING, 5 us SETTLING TIME, 12-BIT DAC, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SOIC-24 |
| 文件頁數(shù)： | 3/11頁 |
| 文件大小： | 215K |
| 代理商： | MAX527AEWG |
M
Low-Power, Dual, 8-Bit, Voltage Output
S erial DAC in 8-Pin S OT 23
_______________________________________________________________________________________
3
Note 1:
The outputs may be shorted to V
DD
or GND if the package power dissipation is not exceeded. Typical short-circuit current to
GND is 70mA.
Note 2:
Reduced digital code range (code 24 through code 232) is due to swing limitations of the output amplifiers. See
Typical
Operating Characteristics
.
Note 3:
Reference input resistance is code-dependent. The lowest input resistance occurs at code 55hex. See the
Reference Input
section.
Note 4:
Guaranteed by design. Not production tested.
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +5.5V, REF = V
DD
, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
DYNAMIC PERFORMANCE
TIMING CHARACTERISTICS
(Figure 3, V
DD
= +2.7V to +5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 4)
V
DD
= +3.6V
V
DD
= +5.5V
100
0.6
220
μA
150
275
All inputs = 0
I
DD
Supply Current
50
μA
V
DD
= +5.5V
Shutdown Supply Current
V
2.7
5.5
V
DD
Supply Voltage Range
nV-s
0.25
All zeros to all ones
Digital Feedthrough
and Crosstalk
μs
To ±
1
2
LSB, C
L
= 100pF
Voltage Output Settling Time
V/μs
0.15
C
L
= 100pF
SR
Voltage Output Slew Rate
MIN
TYP
MAX
UNITS
CONDITIONS
SERIAL INTERFACE TIMING
–—Fall to SCLK Rise Setup Time
CONDITIONS
ns
50
t
CSPWH
–—Pulse Width High
ns
20
t
CL
SCLK Pulse Width Low
ns
20
t
CH
SCLK Pulse Width High
ns
20
t
DH
DIN to SCLK Rise Hold Time
ns
20
t
DS
DIN to SCLK Rise Setup Time
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
ns
ns
50
50
t
CSS
t
CSH
SCLK Rise to –—Rise Setup Time
POWER SUPPLY
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