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參數(shù)資料
| 型號(hào)： | MAX5264 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Octal, 14-Bit Voltage-Output DAC with Parallel Interface for ATE |
| 中文描述： | 八通道、14位、電壓輸出DAC，并行接口，用于ATE |
| 文件頁(yè)數(shù)： | 7/16頁(yè) |
| 文件大?。?/td> | 451K |
| 代理商： | MAX5264 |
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M
Octal, 14-Bit Voltage-Output DAC
with Parallel Interface for ATE
_______________________________________________________________________________________
7
Pin Description
PIN
Device Sense Ground Input for OUTA and OUTB. In normal operation, OUTA and OUTB are referenced
to DUTGNDAB. When
CLR
is low, OUTA and OUTB are forced to the potential on DUTGNDAB.
DUTGNDAB
1
FUNCTION
NAME
DAC A Buffered Output Voltage
OUTA
2
Positive Reference Input for DACs A and B
REFAB+
4
Negative Reference Input for DACs A and B
REFAB-
3
Negative Analog Power Supply. Normally set to -9V. See
Power Supplies, Grounding, and Bypassing
section for bypass requirements.
V
SS
6
Address Bit 2 (MSB)
A2
8
Load Input. Drive this asynchronous input low to transfer the contents of the input latches to their
respective DAC latches. DAC latches are transparent when
LD
is low and latched when
LD
is high.
LD
7
Positive Analog Power Supply. Normally set to +14V. Connect both pins to the supply voltage. See
Grounding and Bypassing
section for bypass requirements.
V
DD
5, 38
Address Bit 1
A1
9
Chip Select. Active-low input.
CS
11
Address Bit 0 (LSB)
A0
10
Write Input. Active-low strobe for conventional memory write sequence. Input data latches are transpar-
ent when
WR
and
CS
are both low.
WR
latches data into the DAC input latch selected by A2–A0 on the
rising edge of
CS
.
WR
12
Digital Power Supply. Normally set to +5V. See
Power Supplies, Grounding, and Bypassing
section for
bypass requirements.
V
CC
13
7
-1.75
12
-8
11
-6
7
4
-3
14
-9
-2
-1
V
REF-
V
DD
V
SS
2.25
-5.5
B
-5
-3.5
9.5
6
E
8
5
6.5
4.5
2
1
V
REF
V
REF+
D
C
A
VOLTAGE
Table 1. Test Conditions for Static Performance Typical Operating Characteristics
Note:
V
REF =
V
REF+
- V
REF-
Clear Input. Drive
CLR
low to force all DAC outputs to the voltage on their respective DUTGND _ _.
Does not affect the status of internal registers. All DACs return to their previous levels when
CLR
goes
high.
Positive Reference Input for DACs G and H
Negative Reference Input for DACs G and H
Data Bits 0–13. Offset binary coding.
D0–D13
15–28
Ground
GND
14
CLR
29
REFGH+
REFGH-
30
31
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