參數(shù)資料
型號(hào): MAX525AEPP
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: Low-Power, Quad, 12-Bit Voltage-Output DAC with Serial Interface
中文描述: SERIAL INPUT LOADING, 12 us SETTLING TIME, 12-BIT DAC, PDIP20
封裝: PLASTIC, DIP-20
文件頁數(shù): 15/16頁
文件大小: 141K
代理商: MAX525AEPP
Power-S upply Considerations
On power-up, all input and DAC registers are cleared
(set to zero code) and DOUT is in Mode 0 (serial data
is shifted out of DOUT on the clock’s falling edge).
For rated MAX525 performance, limit REFAB/REFCD to
less than 1.4V below V
DD
. Bypass V
DD
with a 4.7μF
capacitor in parallel with a 0.1μF capacitor to AGND.
Use short lead lengths and place the bypass capaci-
tors as close to the supply pins as possible.
Grounding and Layout Considerations
Digital or AC transient signals between AGND and
DGND can create noise at the analog outputs. Tie
AGND and DGND together at the DAC, then tie this
point to the highest-quality ground available.
Good printed circuit board ground layout minimizes
crosstalk between DAC outputs, reference inputs, and
digital inputs. Reduce crosstalk by keeping analog
lines away from digital lines. Wire-wrapped boards are
not recommended.
M
Low-Power, Quad, 12-Bit Voltage-Output DAC
with S erial Interfac e
______________________________________________________________________________________
15
DAC_
MAX525
REF_
OUT_
R
I
OUT
2N3904
V
L
FB_
Figure 13. Digitally Programmable Current Source
__________________Pin Configuration
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
V
DD
FBD
OUTD
OUTC
OUTB
OUTA
FBA
AGND
TOP VIEW
FBC
REFCD
PDL
UPO
CS
CL
REFAB
FBB
12
11
9
10
DOUT
DGND
SCLK
DIN
DIP/SSOP
MAX525
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