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參數(shù)資料
| 型號(hào)： | MAX525 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Low-Power, Quad, 12-Bit Voltage-Output DAC with Serial Interface |
| 中文描述： | 低功耗、四路、12位、電壓輸出DAC，串行接口 |
| 文件頁(yè)數(shù)： | 11/16頁(yè) |
| 文件大小： | 141K |
| 代理商： | MAX525 |
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Power-Down Loc kout (
PDL
)
The power-down lockout pin
PDL
disables software
shutdown when low. When in shutdown, transitioning
PDL
from high to low wakes up the part with the output
set to the state prior to shutdown.
PDL
could also be
used to asynchronously wake up the device.
Daisy Chaining Devic es
Any number of MAX525s can be daisy chained by con-
necting the DOUT pin of one device to the DIN pin of
the following device in the chain (Figure 7).
Since the MAX525’s DOUT pin has an internal active
pull-up, the DOUT sink/source capability determines
the time required to discharge/charge a capacitive
load. Refer to the serial-data-out V
OH
and V
OL
specifi-
cations in the Electrical Characteristics.
Figure 8 shows an alternate method of connecting sev-
eral MAX525s. In this configuration, the data bus is
common to all devices; data is not shifted through a
daisy chain. More I/O lines are required in this configu-
ration because a dedicated chip-select input (
CS
) is
required for each IC.
M
Low-Power, Quad, 12-Bit Voltage-Output DAC
with S erial Interfac e
______________________________________________________________________________________
11
CS
SCLK
DIN
DOUT
(MODE 1)
MSB FROM
PREVIOUS WRITE
MSB FROM
PREVIOUS WRITE
COMMAND
EXECUTED
9
8
16
1
A0
A1
D0
C1
C0
D11 D10
D9
D6
D5
D4
D3
D2
D1
D8
D7
DOUT
(MODE 0)
A0
A1
D0
A1
C1
C0
D11 D10
D9
D6
D5
D4
D3
D2
D1
D8
D7
A0
A1
D0
A1
C1
C0
D11 D10
D9
D6
D5
D4
D3
D2
D1
D8
D7
DATA PACKET (N)
DATA PACKET (N-1)
DATA PACKET (N)
DATA PACKET (N-1)
DATA PACKET (N)
Figure 5. Serial-Interface Timing Diagram
SCLK
DIN
DOUT
t
CSO
t
CSS
t
CL
t
CH
t
CP
t
DO1
t
CSW
t
CS1
t
DO2
t
CSH
t
DS
t
DH
CS
Figure 6. Detailed Serial-Interface Timing Diagram
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