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參數(shù)資料
| 型號： | MAX5259 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | EPS300 3/8 BK 48 12/BOX RoHS Compliant: Yes |
| 中文描述： | +3V/+5V、低功耗、8位八通道DAC，帶有滿擺幅輸出緩沖器 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 509K |
| 代理商： | MAX5259 |
M
+3V/+5V, Low-Power, 8-Bit Octal DAC
with Rail-to-Rail Output Buffers
6
_______________________________________________________________________________________
TIMING CHARACTERISTICS (MAX5259)
(V
REF
= +2.5V, GND = 0, C
DOUT
= 100pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V
DD
= +3V and
T
A
= +25
°
C.)
PARAMETER
SYMBOL
t
VDCS
t
LDAC
CONDITIONS
MIN
TYP
5
20
MAX
UNITS
μ
s
ns
V
DD
Rise-to-
CS
Fall-Setup Time
LDAC
Pulse Width Low
40
CS
Rise-to-
LDAC
Fall-Setup Time
(Note 4)
t
CLL
40
ns
CS
Pulse Width High
SCLK Clock Frequency (Note 5)
SCLK Pulse Width High
SCLK Pulse Width Low
CS
Fall-to-SCLK Rise-Setup Time
SCLK Rise-to-
CS
Rise-Hold Time
DIN to SCLK Rise-to-Setup Time
DIN to SCLK Rise-to-Hold Time
t
CSW
f
CLK
t
CH
t
CL
t
CSS
t
CSH
t
DS
t
DH
90
ns
MHz
ns
ns
ns
ns
ns
ns
10
40
40
40
0
40
0
SCLK Rise-to-DOUT Valid
Propagation Delay (Note 6)
t
DO1
200
ns
SCLK Fall-to-DOUT Valid
Propagation Delay (Note 7)
t
DO2
210
ns
CS
Rise-to-SCLK Rise-Setup
Time
t
CS1
40
ns
Note 1:
INL and DNL are measured with R
L
referenced to ground. Nonlinearity is measured from the first code that is greater than or
equal to the maximum offset specification to code FF hex (full scale). (See
DAC Linearity and Voltage Offset
section.)
Note 2:
Output settling time is measured from the 50% point of the rising edge of
CS
to 1/2LSB of the final value of V
OUT
.
Note 3:
Guaranteed by design, not production tested.
Note 4:
If
LDAC
is activated prior to the rising edge of
CS
, it must remain low for t
LDAC
or longer after
CS
goes high.
Note 5:
When DOUT is not used. If DOUT is used, f
CLK
(max) is 4MHz due to SCLK to DOUT propagation delay.
Note 6:
Serial data is clocked-out at SCLK
’
s rising edge (measured from 50% of the clock edge to 20% or 80% of V
DD
).
Note 7:
Serial data is clocked-out at SCLK
’
s falling edge (measured from 50% of the clock edge to 20% or 80% of V
DD
).
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| MAX5259EEE | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 8-Bit 8Ch Precision DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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| MAX5259EEE-T | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 8-Bit 8Ch Precision DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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