參數(shù)資料
型號: MAX5251ACAP
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: +3V, Quad, 10-Bit Voltage-Output DAC with Serial Interface
中文描述: QUAD, SERIAL INPUT LOADING, 12 us SETTLING TIME, 10-BIT DAC, PDSO20
封裝: SSOP-20
文件頁數(shù): 11/16頁
文件大小: 146K
代理商: MAX5251ACAP
M
+3V, Quad, 10-Bit Voltage-Output DAC
with S erial Interfac e
______________________________________________________________________________________
11
Power-Down Loc kout (
PDL
)
The power-down lockout pin
PDL
disables software
shutdown when low. When in shutdown, transitioning
PDL
from high to low wakes up the part with the output
set to the state prior to shutdown.
PDL
could also be
used to wake up the device asynchronously.
Daisy Chaining Devic es
Any number of MAX5251s can be daisy chained by
connecting the DOUT pin of one device to the DIN pin
of the following device in the chain (Figure 7).
Since the MAX5251’s DOUT pin has an internal active
pull-up, the DOUT sink/source capability determines
the time required to discharge/charge a capacitive
load. Refer to the serial-data-out V
OH
and V
OL
specifi-
cations in the Electrical Characteristics.
Figure 8 shows an alternate method of connecting sev-
eral MAX5251s. In this configuration, the data bus is
common to all devices; data is not shifted through a
daisy chain. More I/O lines are required in this configu-
ration because a dedicated chip-select input (
CS
) is
required for each IC.
CS
SCLK
DIN
DOUT
(MODE 1)
MSB FROM
PREVIOUS WRITE
MSB FROM
PREVIOUS WRITE
COMMAND
EXECUTED
9
8
16
1
A0
A1
S0
C1
C0
D9
D8
D7
D4
D3
D2
D1
D0
S1
D6
D5
DOUT
(MODE 0)
A0
A1
S0
A1
C1
C0
D9
D8
D7
D4
D3
D2
D1
D0
S1
D6
D5
A0
A1
S0
A1
C1
C0
D9
D8
D7
D4
D3
D2
D1
D0
S1
D6
D5
DATA PACKET (N)
DATA PACKET (N-1)
DATA PACKET (N)
DATA PACKET (N-1)
DATA PACKET (N)
Figure 5. Serial-Interface Timing Diagram
SCLK
DIN
DOUT
t
CSO
t
CSS
t
CL
t
CH
t
CP
t
DO1
t
CSW
t
CS1
t
DO2
t
CSH
t
DS
t
DH
CS
Figure 6. Detailed Serial-Interface Timing Diagram
相關(guān)PDF資料
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