參數(shù)資料
型號(hào)： MAX521AEWG
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： DAC
英文描述： Dual Differential Drivers and Receivers With +/-15-kV IEC ESD Protection 16-TSSOP -40 to 85
中文描述： SERIAL INPUT LOADING, 6 us SETTLING TIME, 8-BIT DAC, PDSO24
封裝： 0.300 INCH, SOP-24
文件頁(yè)數(shù)： 11/20頁(yè)
文件大小： 274K
代理商： MAX521AEWG
M
Quad/Oc tal, 2-Wire S erial 8-Bit DACs
with Rail-to-Rail Outputs
______________________________________________________________________________________
11
START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a transmis-
sion with a START condition by transitioning SDA from
high to low while SCL is high (Figure 4). When the mas-
ter has finished communicating with the slave, it issues
a STOP condition by transitioning SDA from low to high
while SCL is high. The bus is then free for another
transmission.
Slave Address
The MAX520/MAX521 each have a 7-bit-long slave
address (Figure 5). The first four bits (MSBs) of the slave
address have been factory programmed and are always
0101. In addition, the MAX521 has the next bit factory
programmed to 0. The logic state of the address input
pins (AD0, AD1, and AD2 of the MAX520; AD0 and AD1
of the MAX521) determine the least significant bits of the
7-bit slave address. These input pins may be connected
to V
DD
or DGND, or they may be actively driven by TTL
or CMOS logic levels. There are four possible slave
addresses for the MAX521, and therefore a maximum of
four such devices may be on the bus at one time. The
MAX520 has eight possible slave addresses. The eighth
bit (LSB) in the slave address byte should be low when
writing to the MAX520/MAX521.
The MAX520/MAX521 monitor the bus continuously,
waiting for a START condition followed by its slave
address. When a device recognizes its slave address, it
is ready to accept data.
Command Byte and Output Byte
A command byte follows the slave address. Figure 6
shows the format for the command byte. A command
byte is usually followed by an output byte unless it is
the last byte in the transmission. If it is the last byte, all
bits except PD and RST are ignored. If an output byte
follows the command byte, A0–A2 of the command
byte indicate the digital address of the DAC whose
input data latch receives the digital output data. The
data is transferred to the DAC’s output latch during the
STOP condition following the transmission. This allows
all DACs to be updated and the new outputs to appear
simultaneously (Figure 7).
Setting the PD bit high powers down the MAX520/
MAX521 following a STOP condition (Figure 8a). If a
command byte with PD set high is followed by an out-
put byte, the addressed DAC’s input latch will be
updated and the data will be transferred to the DAC’s
output latch following the STOP condition (Figure 8b). If
the transmission’s last command byte has PD high, the
voltage outputs will not reflect the newly entered data
because the DAC will enter power-down mode when
the STOP condition is detected. When in power-down,
the MAX521’s DAC outputs float, and the MAX520’s
unbuffered outputs look like a 16k
resistor to AGND.
In this mode, the supply current is a maximum of 20μA.
A command byte with the PD bit low returns the
MAX520/MAX521 to normal operation following a STOP
condition, and the voltage outputs reflect the current
output-latch contents (Figures 9a and 9b). Because
each subsequent command byte overwrites the previ-
ous PD bit, only the last command byte of a transmis-
sion affects the power-down state.
SCL
SDA
SLAVE ADDRESS BITS AD2, AD1, AND AD0 CORRESPOND TOTHE LOGIC STATE
OF THE ADDRESS INPUT PINS AD2, AD1, AND AD0.
0
0
1
0 or AD2
1
0
AD1
AD0
LSB
ACK
SLAVE ADDRESS
Figure 5. Address Byte
LSB
MSB
SDA
SCL
R2
R1
R0
RST
PD
A2
A1
A0
ACK
SHUTDOWN MODE. SET TO0 TORETURN TOTHE NORMAL
OPERATIONAL STATE.
WHICH DAC'S INPUT LATCH RECEIVES THE 8 BITS OF DATA IN
THE NEXT BYTE. A2 IS IGNORED BY THE MAX520.
9TH CLOCK PULSE.
Figure 6. Command Byte
SCL
SDA
START CONDITION
STOP CONDITION
Figure 4. All communications begin with a START condition and
end with a STOP condition, both generated by a bus master.
相關(guān)PDF資料
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MAX521BCAG Dual Differential Drivers and Receivers With +/-15-kV IEC ESD Protection 16-TSSOP -40 to 85
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MAX521BEAG Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs
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