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參數(shù)資料
| 型號： | MAX520ACPE |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | DAC |
| 英文描述： | Differential Driver And Receiver Pair 14-SOIC -40 to 85 |
| 中文描述： | SERIAL INPUT LOADING, 2 us SETTLING TIME, 8-BIT DAC, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-16 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 274K |
| 代理商： | MAX520ACPE |
M
Quad/Oc tal, 2-Wire S erial 8-Bit DACs
with Rail-to-Rail Outputs
10
______________________________________________________________________________________
_______________Detailed Desc ription
S erial Interfac e
The MAX520/MAX521 use a simple 2-wire serial interface
requiring only two I/O lines (2-wire bus) of a standard
microprocessor (μP) port. Figure 1 shows the timing dia-
gram for signals on the 2-wire bus. Figure 2 shows the
typical application of the MAX520/MAX521. The 2-wire
bus can have several devices (in addition to the
MAX520/MAX521) attached. The two bus lines (SDA and
SCL) must be high when the bus is not in use. When in
use, the port bits are toggled to generate the appropriate
signals for SDA and SCL. External pull-up resistors are
not required on these lines. The MAX520/MAX521 can
be used in applications where pull-up resistors are
required (such as in I
2
C systems) to maintain compatibil-
ity with the existing circuitry.
The MAX520/MAX521 are receive-only devices and
must be controlled by a bus master device. They oper-
ate at SCL rates up to 400kHz. A master device sends
information to the devices by transmitting their address
over the bus and then transmitting the desired informa-
tion. Each transmission consists of a START condition,
the MAX520/MAX521’s programmable slave-address,
one or more command-byte/output-byte pairs (or a
command byte alone, if it is the last byte in the trans-
mission), and finally, a STOP condition (Figure 3).
The address byte and pairs of command and output
bytes are transmitted between the START and STOP con-
ditions. The SDA state is allowed to change only while
SCL is low. SDA’s state is sampled, and therefore must
remain stable while SCL is high. The only exceptions to
this are the START and STOP conditions. Data is transmit-
ted in 8-bit bytes. Nine clock cycles are required to trans-
fer the data bits to the MAX520/MAX521. Set SDA low
during the 9th clock cycle as the MAX520/MAX521 pull
SDA low during this time. R
C
(Figure 2) limits the current
that flows during this time if SDA stays high for short peri-
ods of time.
MAX520
SDA
R
C
1k
SCL
μ
C
REF0
REF1
REF2
REF3
SDA
AD0
SCL
AD1
AD2
+1V
+4V
+5V
QUAD
DAC
OFFSET ADJUSTMENT
OFFSET ADJUSTMENT
GAIN ADJUSTMENT
GAIN ADJUSTMENT
OUT0
OUT1
OUT2
OUT3
.
.
.
R.
SDA
AD0
SCL
AD1
OCTAL
DAC
+5V
BRIGHTNESS ADJUSTMENT
CONTRAST ADJUSTMENT
REF4
OUT0
OUT1
OUT2
.
.
.
OUT6
OUT7
THRESHOLD
ADJUSTMENTS
+5V
+5V
+12V
MOTOR
MAX521
Figure 2. Typical Application Circuit
START CONDITION
STOP CONDITION
OUTPUT BYTE
COMMAND BYTE
SLAVE ADDRESS BYTE
SCL
SDA
MSB
MSB
MSB
LSB
LSB
LSB
ACK
ACK
ACK
Figure 3. A Complete Serial Transmission
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| MAX520ACWE | Differential Driver And Receiver Pair 14-SOIC -40 to 85 |
| MAX520AEAP | Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs |
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