參數(shù)資料
型號(hào): MAX5202BEUB
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): DAC
英文描述: Low-Cost, Voltage-Output, 16-Bit DACs with Internal Reference in レMAX
中文描述: SERIAL INPUT LOADING, 25 us SETTLING TIME, 16-BIT DAC, PDSO10
封裝: 5 X 3 MM, MICRO, SOP-10
文件頁(yè)數(shù): 5/13頁(yè)
文件大小: 288K
代理商: MAX5202BEUB
M
Low-Cost, Voltage-Output, 16-Bit DACs with
Internal Reference in μMAX
_______________________________________________________________________________________
5
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INTERNAL REFERENCE
V
Output Voltage
T
A
= +25°C
T
A
= 0°C to +70°C
T
A
= -40°C to +105°C
1.46
1.5
±15
±20
1.54
V
V
REF
Tempco
ppm/°C
DIGITAL INPUTS (DIN, SCLK,
CS
,
CLR
,
LDAC
)
Input High Voltage
Input Low Voltage
Input Hysteresis
Input Leakage
Input Capacitance
POWER REQUIREMENTS
Positive Power Supply
Positive Supply Current
Shutdown Supply Current
TIMING CHARACTERISTICS
SCLK Frequency
SCLK Clock Period
SCLK Pulse Width High
SCLK Pulse Width Low
DIN Setup Time
DIN Hold Time
CS
Fall to SCLK Rise Setup Time
SCLK Rise to
CS
Rise Hold Time
SCLK Rise to
CS
Fall Ignore
CS
Rise to SCLK Rise Ignore
LDAC
Pulse Width
CS
Rise to
LDAC
Low Setup
SCLK Fall to
CS
Fall Ignore
C S
P ul se W d h Low for S hutd ow n
CS
Pulse Width High
V
IH
V
IL
V
HYST
I
IN
C
IN
2.1
V
V
0.6
200
mV
μA
pF
Digital inputs = 0 or V
DD
±1
15
V
DD
I
DD
I
SHDN
2.7
3.6
1.5
10
V
All digital inputs at 0 or V
DD
(Note 5)
All digital inputs at 0 or V
DD
0.8
1
mA
μA
f
SCLK
t
CP
t
CH
t
CL
t
DS
t
DH
t
CSS
t
CSH
t
CS0
t
CS1
t
LDAC
t
LDACS
t
CSOL
t
CSWL
t
CSWH
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
40
40
40
0
40
0
10
40
40
40
10
40
100
Note 1:
Static performance tested at V
DD
= +5.0V (MAX5200/MAX5201) and at V
DD
= +3.0V (MAX5202/MAX5203).
Note 2:
INL and DNL are guaranteed for outputs between 0.5V to (V
DD
- 0.5V).
Note 3:
Guaranteed monotonic.
Note 4:
V
REF
= 2.5V (MAX5200/MAX5201) and V
REF
= 1.5V (MAX5202/MAX5203).
Note 5:
R
L
=
, digital inputs are at V
DD
or DGND.
ELECTRICAL CHARACTERISTICS—MAX5202/MAX5203 (continued)
(V
DD
= +2.7V to +3.6V, f
SCLK
= 10MHz (50% duty cycle), output load = 10k
in parallel with 250pF, T
A
= T
MIN
to T
MAX
, unless otherwise
noted. Typical values are at T
A
= +25°C.)
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