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參數(shù)資料
| 型號： | MAX520-MAX521 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs |
| 中文描述： | 四路/八路，2線串行8位DAC與軌至軌輸出 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大小： | 274K |
| 代理商： | MAX520-MAX521 |
M
Quad/Oc tal, 2-Wire S erial 8-Bit DACs
with Rail-to-Rail Outputs
______________________________________________________________________________________
13
Setting the RST bit high clears all DAC input latches.
The DAC outputs remain unchanged until a STOP con-
dition is detected (Figure 10a). If a reset is issued, the
following output byte is ignored. Subsequent pairs of
command/output bytes overwrite the input latches
(Figure 10b).
All changes made during a transmission affect the
MAX520/MAX521’s outputs only when the transmission
ends and a STOP has been recognized. The R0, R1,
and R2 bits are reserved bits that must be set to zero.
I
2
C Compatibility
The MAX520/MAX521 are fully compatible with existing
I
2
C systems. SCL and SDA are high-impedance inputs;
SDA has an open drain which pulls the data line low
during the 9th clock pulse. Figure 11 shows a typical
I
2
C application.
Additional START Conditions
It is possible to interrupt a transmission to a MAX520/
MAX521 with a new START (repeated start) condition
(perhaps addressing another device), which leaves the
input latches with data that has not been transferred to
the output latches (Figure 12). Only the currently
addressed device will recognize a STOP condition and
transfer data to its output latches. If the device is left
with data in its input latches, the data can be trans-
ferred to the output latches the next time the device is
addressed, as long as it receives at least one com-
mand byte and a STOP condition.
( )
SET TO 0
( )
SET TO 0
( )
SDA
0
START
CONDITION
ADDRESS BYTE
ACK
1
0
1
AD1 AD0 0
0
0 0 0 1 0
0
(RST)
(RST)
1
STOP
CONDITION
COMMAND BYTE
ACK
( )
SET TO 0
ALL INPUT LATCHES
SDA
0
START
CONDITION
ADDRESS BYTE
ACK
1
0
1
AD1 AD0 0 0 0
0
0
0
0
0
STOP
CONDITION
COMMAND BYTE
ACK
"DUMMY"
OUTPUT BYTE
ACK
(a)
(b)
ALL DAC OUTPUTS SET TO0 UNLESS
CHANGED BY ADDITIONAL COMMAND
BYTE/OUTPUT BYTE PAIRS
NOTE: X = DONT CARE
ADDITIONAL
COMMAND BYTE/
OUTPUT BYTE PAIRS
X X X
X X X
X X X X X X X X
0 OR AD2
0 OR AD2
Figure 10. Resetting DAC Outputs
MAX520
SDA SCL
μ
C
SDA
SCL
E
2
PROM
XICOR
X24C04
SDA
AD0
SCL
AD1
AD2
QUAD
DAC
SDA
AD0
SCL
AD1
OCTAL
DAC
+5V
MAX521
Figure 11. Typical I
2
C Application Circuit
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