參數(shù)資料
型號(hào)： MAX518BCSA
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： DAC
英文描述： 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs
中文描述： DUAL, SERIAL INPUT LOADING, 6 us SETTLING TIME, 8-BIT DAC, PDSO8
封裝： 0.150 INCH, SO-8
文件頁(yè)數(shù)： 11/16頁(yè)
文件大?。?/td> 178K
代理商： MAX518BCSA
M
2-Wire S erial 8-Bit DACs with
Rail-to-Rail Outputs
______________________________________________________________________________________
11
Furthermore if the transmission’s last command byte
has PD high, the output latches are updated, but volt-
age outputs will not reflect the newly entered data
because the DAC enters power-down mode when the
STOP condition is detected. When in power-down, the
DAC outputs float. In this mode, the supply current is a
maximum of 20μA. A command byte with the PD bit low
returns the MAX517/MAX518/MAX519 to normal opera-
tion following a STOP condition, with the voltage out-
puts reflecting the output-latch contents (Figures 10a
and 10b). Because each subsequent command byte
overwrites the previous PD bit, only the last command
byte of a transmission affects the power-down state.
Setting the RST bit high clears the DAC input latches.
The DAC outputs remain unchanged until a STOP con-
dition is detected (Figure 11a). If a reset is issued, the
following output byte is ignored. Subsequent pairs of
command/output bytes overwrite the input latches
(Figure 11b).
All changes made during a transmission affect the
MAX517/MAX518/MAX519’s outputs only when the
transmission ends and a STOP has been recognized.
The R0, R1, and R2 bits are reserved and must be set
to zero.
I
2
C Compatibility
The MAX517/MAX518/MAX519 are fully compatible
with existing I
2
C systems. SCL and SDA are high-
impedance inputs; SDA has an open drain that pulls
the data line low during the 9th clock pulse. Figure 12
shows a typical I
2
C application.
( )
SET TO 0.
( )
SET TO 0.
( )
SDA
0
START
CONDITION
ADDRESS BYTE
ACK
1
0
1
or
AD3
1
or
AD2AD1AD0 0
0
0 0 0 1 0
0
(RST)
(RST)
1
STOP
CONDITION
COMMAND BYTE
ACK
( )
SET TO 0.
SDA
0
START
CONDITION
ADDRESS BYTE
ACK
1
0
1
or
AD3
1
or
AD2AD1AD0 0 0 0
0
0
0
0
0
STOP
CONDITION
COMMAND BYTE
ACK
"DUMMY"
OUTPUT BYTE
ACK
(a)
(b)
DAC OUTPUTS SET TO0 UNLESS
CHANGED BY ADDITIONAL COMMAND
BYTE/OUTPUT BYTE PAIRS.
NOTE: X = DONT CARE
ADDITIONAL
COMMAND BYTE/
OUTPUT BYTE PAIRS
X X X
X X X
X X X X X X X X
Figure 11. Resetting DAC Outputs
LATCH SET TO0.
SDA
0
START
CONDITION
ADDRESS BYTE
ACK
1
0
1
or
AD3
1
or
AD2AD1AD0 0
0
0
0 0 0 0 0
(PD)
(PD)
0
STOP
CONDITION
COMMAND BYTE
ACK
NORMAL OPERATION
( )
DAC0 INPUT
SDA
0
START
CONDITION
ADDRESS BYTE
ACK
1
0
1
or
AD3
1
or
AD2AD1AD0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
STOP
CONDITION
( )
COMMAND BYTE
(ADDRESSING DAC0)
ACK
OUTPUT BYTE
(SET TO0)
ACK
(a)
(b)
DAC0 SET TO0.
NOTE: X = DONT CARE
X X X
X X
Figure 10. Returning to Normal Operation from Power-Down
相關(guān)PDF資料
PDF描述
MAX518BESA 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs
MAX517-MAX519 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs
MAX517BMJA 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs
MAX518BMJA 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs
MAX5190 8-Bit, 40MHz, Current/Voltage-Output DACs
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