參數(shù)資料
型號(hào): MAX5175AEEE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: Low-Power, Serial, 12-Bit DACs with Force/Sense Voltage Output
中文描述: SERIAL INPUT LOADING, 12 us SETTLING TIME, 12-BIT DAC, PDSO16
封裝: 0.150 INCH, 0.025 INCH PITCH, QSOP-16
文件頁(yè)數(shù): 12/16頁(yè)
文件大?。?/td> 255K
代理商: MAX5175AEEE
M
Low-Power, S erial, 12-Bit DACs with
Forc e/S ense Voltage Output
12
______________________________________________________________________________________
S erial-Data Output (DOUT )
The serial-data output (DOUT) is the internal shift regis-
ter’s output and allows for daisy-chaining of multiple
devices as well as data readback (see Applications
Information. By default upon start-up, data shifts out of
DOUT on the serial clock’s rising edge (Mode 0) and
provides a lag of 16 clock cycles, thus maintaining SPI,
QSPI, and MICROWIRE compatibility. However, if the
device is programmed for Mode 1, then the output data
lags DIN by 16.5 clock cycles and is clocked out on the
serial clock’s rising edge. During shutdown, DOUT
retains its last digital state prior to shutdown.
User-Programmable Logic Output (UPO)
The UPO allows control of an external device through
the serial interface, thereby reducing the number of
microcontroller I/O pins required. During power-down,
this output will retain its digital state prior to shutdown.
When
CLR
is pulled low, UPO will reset to its pro-
grammed default state. See Table 1 for specific com-
mands to control the UPO.
Reset (RS ) and Clear (
CLR
)
The MAX5175/MAX5177 offers a clear pin (
CLR
) which
resets the output voltage. If RST = DGND, then
CLR
resets the output voltage to the minimum voltage (0 if
no offset is introduced). If RST = V
DD
, then
CLR
resets
the output voltage to midscale. In either case,
CLR
will
reset UPO to its programmed default state.
CS
SCLK
DIN
COMMAND
EXECUTED
9
8
16
1
C1
C2
S0
C0
D9
D8
D7
D6
D3
D2
D1
D0
S2
S1
D5
D4
Figure 4. Serial-Interface Timing Diagram
CS
SCLK
DIN
DOUT
t
CSW
t
CS1
t
CSH
t
CSS
t
CSO
t
D02
t
CH
t
CL
t
CP
t
D01
t
DS
t
DH
Figure 5. Detailed Serial-Interface Timing Diagram
相關(guān)PDF資料
PDF描述
MAX5175BEEE Low-Power, Serial, 12-Bit DACs with Force/Sense Voltage Output
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