參數(shù)資料
型號: MAX5171BEEE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: Low-Power, Serial, 14-Bit DACs with Force/Sense Voltage Output
中文描述: SERIAL INPUT LOADING, 12 us SETTLING TIME, 14-BIT DAC, PDSO16
封裝: 0.150 INCH, 0.025 INCH PITCH, QSOP-16
文件頁數(shù): 9/16頁
文件大?。?/td> 256K
代理商: MAX5171BEEE
M
Low-Power, S erial, 14-Bit DACs
with Forc e/S ense Voltage Output
_______________________________________________________________________________________
9
Typic al Operating Charac teristic s (c ontinued)
(MAX5171: V
DD
= +5V, V
REF
= 2.5V; MAX5173: V
DD
= +3V, V
REF
= 1.25V; C
L
= 100pF, FB = OUT, code = 3FFF hex, T
A
= +25°C,
unless otherwise noted.)
-25.0
-20.0
-10.0
-15.0
-5.0
0
0
1000
FREQUENCY (kHz)
500
1500
2000
2500
3000
REFERENCE VOLTAGE
INPUT FREQUENCY RESPONSE
M
G
V
REF
= 0.67Vp-p + 1.25V
DC
V
DD
(1V/div)
V
OUT
(10mV/div)
AC-COUPLED
START-UP GLITCH
M
50ms/div
Pin Desc ription
Voltage Output. High impedance in shutdown. Output voltage is limited to V
DD
.
Reset Mode Select (digital input). Connect to V
DD
to select midscale reset output value. Connect to DGND
to select 0 reset output value.
OUT
2
Power-Down Lockout (digital input). Connect to V
DD
to allow shutdown. Connect to DGND to disable shut-
down.
PDL
4
RS
3
Chip-Select Input (digital input)
Serial-Data Input (digital input). Data is clocked in on the rising edge of SCLK.
CS
DIN
6
7
Serial Clock Input (digital input)
Digital Ground
SCLK
DGND
8
9
Clear DAC (digital input). Clears the DAC to its predetermined output state as set by RS.
CLR
5
Serial-Data Output
User-Programmable Output. State is set by serial input.
DOUT
UPO
10
11
Shutdown (digital input). Pulling SHDN high when
PDL
= V
DD
places the chip in shutdown mode with a
maximum shutdown current 0f 10μA.
SHDN
12
Reference Input. Maximum V
REF
is V
DD
- 1.4V.
No Connection
REF
N.C.
14
15
PIN
Positive Supply. Bypass to AGND with a 4.7μF capacitor in parallel with a 0.1μF capacitor.
V
DD
16
Feedback Input
FB
1
FUNCTION
NAME
Analog Ground
AGND
13
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