參數(shù)資料
型號(hào): MAX5165NECM
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): 運(yùn)動(dòng)控制電子
英文描述: 32-Channel Sample/Hold Amplifier with a Single Multiplexed Input
中文描述: SAMPLE AND HOLD AMPLIFIER, 2.5 us ACQUISITION TIME, PQFP48
封裝: TQFP-48
文件頁(yè)數(shù): 7/12頁(yè)
文件大小: 149K
代理商: MAX5165NECM
Sample Mode
Driving M3–M0 low (one at a time) selects sample
mode (Tables 1, 2). During sample mode, the selected
multiplexer channel connects to IN, allowing the hold
capacitor to acquire the input signal. To guarantee an
accurate sample, maintain sample mode for at least
4μs. The output of the S/H amplifier tracks the input
after 4μs. Only the addressed channel on the selected
multiplexer samples the input; all other channels remain
in hold mode.
Hold Mode
Driving M3–M0 high selects hold mode. Hold mode dis-
ables the multiplexer and disconnects all eight chan-
nels on the 1-to-8 multiplexer from the input. When a
channel is disconnected, the hold capacitor maintains
the sampled voltage at the output with a 1mV/sec
droop rate (towards V
DD
).
Hold Step
When switching between sample mode and hold mode,
the voltage of the hold capacitor changes due to
charge injection from stray capacitance. This voltage
change, called hold step, is minimized by limiting the
amount of stray capacitance seen by the hold capaci-
tor. The MAX5165 limits the hold step to 0.25mV (typ).
An output capacitor to ground can be used to filter out
this small hold-step error.
Output
The MAX5165 contains an output buffer for each multi-
plexer channel (32 total), so the hold capacitor sees a
high-impedance input, reducing the droop rate. The
capacitor droops at a 1mV/sec (typ) rate while in hold
mode. The buffer also provides a low output imped-
ance; however, the device contains output resistors in
series with the buffer output (Figure 1) for selected out-
put filtering. To provide greater design flexibility, the
MAX5165 is available with an R
O
of 50
, 500
, or 1k
.
Note: Output loads increase the analog supply cur-
rent (I
DD
and I
SS
).
Excessive loading of the output(s)
damages the device by consuming more power than the
device will dissipate (see
Absolute Maximum Ratings
).
The resistor-divider formed by the output resistor (R
OUT
)
and load impedance (R
L
) scales the sampled voltage
(V
SAMP
). Determine the output voltage (V
OUT_
) as follows:
Voltage Gain = A
V
= R
L
/ (R
L
+ R
OUT
)
V
OUT_
= V
SAMP
·
A
V
The maximum output voltage range depends on the
analog supply voltages available, and the scaling factor
used:
(V
SS
+ 0.75V)
·
A
V
V
OUT_
(V
DD
- 2.4V)
·
A
V
when R
L
=
, then A
V
= 1 and this equation becomes:
(V
SS
+ 0.75V)
V
OUT
(V
DD
- 2.4V)
M
32-Channel Sample/Hold Amplifier
with a Single Multiplexed Input
_______________________________________________________________________________________
7
0
0
0
0
1
1
Table 1. Output Selection
Table 2. Mode Selection
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
ADDRESS
A1
0
1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT0
OUT1
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OUT8
OUT9
OUT18
OUT19
OUT20
OUT21
OUT22
OUT23
OUT16
OUT17
OUTPUT SELECTED
MUX1
OUT26
OUT27
OUT28
OUT29
OUT30
OUT31
OUT24
OUT25
A2
A0
MUX0
MUX2
MUX3
0 = Logic Low, 1 = Logic High
0
1
Sample mode enabled on selected
analog multiplexer and channel
(Table 1).
Hold mode enabled on selected
analog multiplexer and channel
(Table 1).
MODE-SELECT
INPUTS (M3–M0)
ACTION
0 = Logic Low, 1 = Logic High
* Only one M_ input asserted low; all others must be logic high
to meet the timing specification (see Single vs. Simultaneous
Sampling section).
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