參數(shù)資料
型號: MAX5158MJE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: Low-Power, Dual, 10-Bit, Voltage-Output DACs with Serial Interface
中文描述: DUAL, SERIAL INPUT LOADING, 16 us SETTLING TIME, 10-BIT DAC, CDIP16
封裝: 0.300 INCH, CERDIP-16
文件頁數(shù): 3/16頁
文件大?。?/td> 181K
代理商: MAX5158MJE
M
Low-Power, Dual, 10-Bit, Voltage-Output DACs
with S erial Interfac e
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS—MAX5158 (continued)
(V
DD
= +5V ±10%, V
REFA
= V
REFB
= 2.048V, R
L
= 10k
, C
L
= 100pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are
at T
A
= +25°C (OS_ tied to AGND for a gain of +2V/V).)
Note 1:
Accuracy is specified from code 2 to code 1023.
Note 2:
Accuracy is better than 1LSB for V
OUT
_ greater than 6mV and less than V
DD
- 50mV. Guaranteed by PSRR test at the
end points.
Note 3:
Digital inputs are set to either V
DD
or DGND, code = 0000 hex, R
L
=
.
Note 4:
SCLK minimum clock period includes rise and fall times.
CS
= V
DD
, f
DIN
= 100kHz, V
SCLK
= 5Vp-p
I
SOURCE
= 2mA
I
SINK
= 2mA
(Note 4)
(Note 3)
(Note 3)
ns
ns
Rail-to-rail (Note 2)
To 1/2LSB of full-scale, V
STEP
= 4V
40
40
t
CL
t
CSS
SCLK Pulse Width Low
CS
Fall to SCLK Rise Setup Time
CONDITIONS
ns
40
t
CH
SCLK Pulse Width High
nV-s
5
Digital Crosstalk
nV-s
5
Digital Feedthrough
μs
25
Time Required to Exit Shutdown
k
24
34
R
OS_
OSA or OSB Input Resistance
ns
100
t
CP
SCLK Clock Period
μA
0
±1
Reference Current in Shutdown
μA
2
10
I
DD(SHDN)
Power-Supply Current
in Shutdown
mA
0.5
0.65
I
DD
Power-Supply Current
V
4.5
5.5
V
DD
Positive Supply Voltage
ns
ns
40
0
t
DS
t
DH
SDI Setup Time
SDI Hold Time
ns
V
V
V
DD
- 0.5
V
OH
V
OL
Output High Voltage
Output Low Voltage
0
t
CSH
SCLK Rise to
CS
Rise Hold Time
C
LOAD
= 200pF
V
0 to V
DD
Output Voltage Swing
μs
8
Output Settling Time
C
LOAD
= 200pF
ns
80
0.13
0.4
V/μs
0.75
SR
Voltage Output Slew Rate
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
t
DO2
SCLK Fall to DOUT
Valid Propagation Delay
SCLK Rise to
CS
Fall Delay
ns
80
t
DO1
SCLK Rise to DOUT
Valid Propagation Delay
ns
100
t
CSW
CS
Pulse Width High
ns
40
t
CS1
CS
Rise to SCLK Rise Hold
ns
10
t
CS0
DIGITAL OUTPUTS (DOUT, UPO)
DYNAMIC PERFORMANCE
POWER SUPPLIES
TIMING CHARACTERISTICS
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