參數(shù)資料
型號: MAX5150BEEE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: Low-Power, Dual, 13-Bit Voltage-Output DACs with Serial Interface
中文描述: DUAL, SERIAL INPUT LOADING, 16 us SETTLING TIME, 13-BIT DAC, PDSO16
封裝: 0.150 INCH, 0.025 INCH PITCH, QSOP-16
文件頁數(shù): 5/16頁
文件大小: 188K
代理商: MAX5150BEEE
M
Low-Power, Dual, 13-Bit Voltage-Output DACs
with S erial Interfac e
_______________________________________________________________________________________
5
Note 4:
Accuracy is specified from code 20 to code 8191.
Note 5:
Accuracy is better than 1LSB for V
OUT
greater than 6mV and less than V
DD
- 80mV. Guaranteed by PSRR test at the end
points.
Note 6:
Digital inputs are set to either V
DD
or DGND, code = 0000 hex, R
L
=
.
ELECTRICAL CHARACTERISTICS—MAX5151 (continued)
(V
DD
= +2.7V to +3.6V, V
REFA
= V
REFB
= 1.25V, R
L
= 10k
, C
L
= 100pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values
are at T
A
= +25°C (OS_ pins tied to AGND for a gain of +2).)
C
LOAD
= 200pF
ns
120
t
DO2
SCLK Fall to DOUT Valid
Propagation Delay
ns
100
t
CSW
CS
Pulse Width High
ns
40
t
CS1
CS
Rise to SCLK Rise Hold
ns
10
t
CS0
SCLK Rise to
CS
Fall Delay
CONDITIONS
UNITS
(Note 6)
mA
0.45
0.6
I
DD
Power-Supply Current
(Note 6)
μA
1
8
I
DD (SHDN)
Power-Supply Current
in Shutdown
μA
MIN
TYP
MAX
0
±1
Reference Current in Shutdown
TIMING CHARACTERISTICS
ns
ns
ns
100
40
40
SYMBOL
PARAMETER
t
CP
t
CH
t
CL
SCLK Clock Period
SCLK Pulse Width High
SCLK Pulse Width Low
ns
40
t
CSS
CS
Fall to SCLK Rise
Setup Time
ns
ns
ns
0
t
CSH
t
DS
t
DH
SCLK Rise to
CS
Rise Hold Time
SDI Setup Time
SDI Hold Time
50
0
C
LOAD
= 200pF
ns
120
t
DO1
SCLK Rise to DOUT Valid
Propagation Delay
V
2.7
3.6
V
DD
Positive Supply Voltage
POWER SUPPLIES
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