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參數(shù)資料
| 型號： | MAX514 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | CMOS Quad.12-Bit.Serial-Input Multiplying DAC |
| 中文描述： | CMOS、四路、12位、串行輸入乘法DAC |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 298K |
| 代理商： | MAX514 |
M
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS—MAX5121 (+3V) (continued)
(V
DD
= +3V ±10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, R
L
= 5k
, C
L
= 100pF, T
A
= T
MIN
to
T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
CONDITIONS
SYMBOL
PARAMETER
V
IN
= 0 or V
DD
I
IN
Input Leakage Current
C
IN
Input Capacitance
DIGITAL OUTPUTS
To ±0.5LSB, V
STEP
= 2V
CS
= V
DD
, f
SCLK
= 100kHz,
V
SCLK
= 3Vp-p
μA
3
20
I
SHDN
Power-Supply Current in Shutdown
μA
500
600
I
DD
Power-Supply Current (Note 5)
V
2.7
3.6
V
DD
Power-Supply Voltage (Note 5)
nV-s
5
Digital Feedthrough
ms
2
Time Required to Exit Shutdown
k
83
121
R
OS
OS Input Resistance
μs
V
20
Output Settling Time
Output Voltage Swing (Note 4)
0 to V
DD
UNITS
μA
pF
MIN
-1
TYP
0.001
8
MAX
1
I
SINK
= 2mA
V
0.13
0.4
V
OL
Output Low Voltage
DYNAMIC PERFORMANCE
I
SOURCE
= 2mA
V
V
DD
- 0.5
V
OH
Output High Voltage
V/μs
0.6
SR
Voltage Output Slew Rate
TIMING CHARACTERISTICS—MAX5120 (+5V)
(V
DD
= +5V ±10%, OS = AGND = DGND = 0V, 33nF capacitor at REFADJ, internal reference, R
L
= 5k
, C
L
= 100pF, T
A
= T
MIN
to
T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
SYMBOL
PARAMETER
ns
ns
ns
ns
40
0
40
0
t
CSS
t
CSH
t
DS
t
DH
CS
Fall to SCLK Rise Setup Time
SCLK Rise to
CS
Rise Hold Time
SDI Setup Time
SDI Hold Time
ns
40
t
CL
SCLK Pulse Width Low
CONDITIONS
ns
ns
100
40
t
CP
t
CH
SCLK Clock Period
SCLK Pulse Width High
ns
ns
10
40
t
CS0
t
CS1
SCLK Rise to
CS
Fall Delay Time
CS
Rise to SCLK Rise Hold Time
UNITS
MIN
TYP
MAX
ns
100
t
CSW
CS
Pulse Width High
C
LOAD
= 200pF
ns
80
t
DO1
SCLK Rise to DOUT Valid
Propagation Delay Time
C
LOAD
= 200pF
ns
80
t
DO2
SCLK Fall to DOUT Valid
Propagation Delay Time
POWER REQUIREMENTS
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