參數(shù)資料
型號(hào): MAX512CPD
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: Low-Cost, Triple, 8-Bit Voltage-Output DACs with Serial Interface
中文描述: SERIAL INPUT LOADING, 70 us SETTLING TIME, 8-BIT DAC, PDIP14
封裝: PLASTIC, DIP-14
文件頁數(shù): 8/16頁
文件大?。?/td> 179K
代理商: MAX512CPD
M
Low-Cost, Triple, 8-Bit Voltage-Output DACs
with S erial Interfac e
8
_______________________________________________________________________________________
A
TIME EXITING SHUTDOWN MODE
20
μ
s/div
V
DD
= 3V, V
SS
= 0V, REFAB = V
DD,
R
L
= k
, C
L
= 0.1
μ
F
DAC LOADED WITH ALL 1s
: OUTA, 1V/div
B
_____________________________Typic al Operating Charac teristic s (c ontinued)
(T
A
= +25°C, unless otherwise noted.)
OUTA,
200
μ
V/div
OUTPUT VOLTAGE NOISE DC TO1MHz
2ms/div
DIGITAL CODE = 80, REFAB = V
DD,
NOLOAD
______________________________________________________________Pin Desc ription
DAC B Output Voltage (Buffered). Resets to full scale.
Connect 0.01μF capacitor or greater to GND.
OUTB
9
DAC C Output Voltage (Unbuffered). Resets to zero.
OUTC
10
DAC C Reference Voltage
REFC
11
DAC A/B Reference Voltage
REFAB
12
Internally connected. Do not make connections to this pin.
I.C.
13
Positive Power Supply (2.7V to 5.5V). Bypass with 0.22μF to GND.
V
DD
5
Ground
GND
6
Negative Power Supply 0V or (-1.5V to -5.5V). Tie to GND for single supply operation. If a negative supply
is applied, bypass with 0.22μF to GND.
V
SS
7
DAC A Output Voltage (Buffered). Resets to full scale.
Connect 0.1μF capacitor or greater to GND.
OUTA
8
Asynchronous reset input (active low). Clears all registers to their default state (FFhex for DAC A and
DAC B registers); all other registers are reset to 0 (including the input shift register).
–————–
4
Serial Clock Input. Data is clocked in on the rising edge of SCLK.
SCLK
3
PIN
Chip Select (active low). Enables data to be shifted into the 16-bit shift register. Programming commands
–—–
2
Serial Data Input of the 16-bit shift register. Data is clocked into the register on the rising edge of SCLK.
DIN
1
FUNCTION
NAME
14
LOUT
Logic Output (latched)
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