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參數(shù)資料
| 型號： | MAX5116 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial Interface |
| 中文描述： | 非易失、四路、8位DAC，帶有2線串行接口 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 459K |
| 代理商： | MAX5116 |
M
Nonvolatile, Quad, 8-Bit DACs with 2-Wire Serial
Interface
12
______________________________________________________________________________________
Serial Interface
The MAX5115/MAX5116 feature an I
2
C-compatible, 2-
wire serial interface consisting of a bidirectional serial
data line (SDA) and a serial clock line (SCL). SDA and
SCL facilitate bidirectional communication between the
MAX5115/MAX5116 and the master at rates up to
400kHz (Figure 4). The master (typically a microcon-
troller) initiates data transfer on the bus and generates
SCL. SDA and SCL require pullup resistors (2.4k
or
greater; see the
Typical Operating Circuit
). Optional
resistors (24
) in series with SDA and SCL protect the
device inputs from high-voltage spikes on the bus lines.
Series resistors also minimize crosstalk and undershoot
of the bus signals.
I
2
C Compatibility
The MAX5115/MAX5116 are compatible with existing
I
2
C systems. SCL and SDA are high-impedance inputs;
SDA has an open-drain output. The
Typical Operating
Circuit
shows an I
2
C application. The communication
protocol supports standard I
2
C 8-bit communications.
The general call address is ignored, and CBUS formats
are not supported. The devices’ addresses are com-
patible with 7-bit I
2
C addressing protocol only. No 10-
bit address formats are supported.
Bit Transfer
One data bit transfers during each SCL rising edge.
Nine clock cycles are required to transfer the data into
or out of the MAX5115/MAX5116. The data on SDA
must remain stable during the high period of the SCL
clock pulse. Changes in SDA while SCL is high are
read as control signals (see the
START and STOP
Conditions
section). Both SDA and SCL idle high.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA with SCL high.
The master terminates a transmission with a STOP condi-
tion (P), a low-to-high transition on SDA while SCL is high
(Figure 5). A START condition from the master signals
the beginning of a transmission to the MAX5115/
MAX5116. The master terminates transmission by issu-
ing a STOP condition. The STOP condition frees the bus.
If a REPEATED START condition (Sr) is generated
instead of a STOP condition, the bus remains active.
Early STOP Conditions
The MAX5115/MAX5116 recognize a STOP condition at
any point during transmission except if a STOP condi-
tion occurs in the same high pulse as a START condi-
tion (Figure 6). This condition is not a legal I
2
C format.
REPEATED START Conditions
A REPEATED START (Sr) condition is used when the
bus master is writing to several I
2
C devices and does
not want to relinquish control of the bus. The
MAX5115/MAX5116 serial interface supports continu-
ous write operations with an Sr condition separating
them. Continuous read operations require Sr conditions
because of the change in direction of data flow.
t
HD:STA
t
HIGH
t
R
t
F
t
HD:STA
S
Sr
ACK
SCL
SDA
t
SU:STA
t
SU:STO
t
R
t
F
t
BUF
t
LOW
t
SU:DAT
t
HD:DAT
P
S
PARAMETERS ARE MEASURED FROM 30% TO 70%.
Figure 4. 2-Wire Serial-Interface Timing Diagram
S
P
Sr
SCL
SDA
Figure 5. START and STOP Conditions
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| MAX5116EEE-T | 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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