參數(shù)資料
型號： MAX510ACPE
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： DAC
英文描述： Low Power 5V RS232 Dual Driver/Receiver with 0.1?μF Capacitors; Package: SO; No of Pins: 16; Temperature Range: -40?°C to 85?°C
中文描述： QUAD, SERIAL INPUT LOADING, 6 us SETTLING TIME, 8-BIT DAC, PDIP16
封裝： PLASTIC, DIP-16
文件頁數(shù)： 4/20頁
文件大?。?/td> 235K
代理商： MAX510ACPE
M
Quad, S erial 8-Bit DACs
with Rail-to-Rail Outputs
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD= +5V ±10%, VSS= 0V to -5.5V, VREF= 4V, AGND = DGND = 0V, RL= 10k
, CL= 100pF, TA= TMINto TMAX,
unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Positive Supply Voltage
Negative Supply Voltage
SYMBOL
4.5
-5.5
5.5
0
10
12
V
V
For specified performance
For specified performance
Outputs unloaded, all
digital inputs = 0V or V
DD
V
DD
V
SS
5
5
Positive Supply Current
mA
I
DD
Negative Supply Current
mA
I
SS
5
10
MAX5_ _C/E
MAX5_ _M
MAX5_ _C/E
5
12
MAX5_ _M
V
SS
= -5V ±10%, outputs
unloaded, all digital
inputs = 0V or V
DD
Note 1:
Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.
Note 2:
Input capacitance is code dependent. The highest input capacitance occurs at code = 00 hex.
Note 3:
VREF = 4V
p-p
, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the
code of all other DACs to 00 hex.
Note 4:
VREF = 4V
p-p
, 10kHz. DAC code = 00 hex.
Note 5:
Guaranteed by design.
Note 6:
Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.
TIMING CHARACTERISTICS
(VDD= +5V ±10%, VSS= 0V to -5V, VREF= 4V, AGND = DGND = 0V, CL= 50pF, TA= TMINto TMAX, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
40
50
0
TYP
20
25
MAX
UNITS
CLR
Pulse Width Low
SYMBOL
50
25
ns
MAX5_ _M
MAX5_ _C/E
MAX5_ _M
(Notes 7, 8)
t
CLW
ns
MAX5_ _C/E
40
20
SCLK Fall to
CS
Rise Hold Time
SCLK Rise to
CS
Rise Hold Time
0
ns
ns
t
CSH2
t
CSH1
SCLK Fall to
CS
Fall Hold Time
0
ns
(Note 7)
MAX5_ _C/E
MAX5_ _M
t
CSH0
40
50
10
10
100
100
MAX5_ _C/E
MAX5_ _M
MAX5_ _C/E
MAX5_ _M
40
50
40
50
MAX5_ _C/E
MAX5_ _M
20
20
12.5
10
MAX5_ _C/E
MAX5_ _M
DIN to SCLK Rise Hold Time
0
ns
t
DH
(Note 9)
40
LDAC
Pulse Width Low
ns
t
LDW
t
CLL
CS
Rise to
LDAC
Fall Setup Time
40
50
MAX5_ _C/E
MAX5_ _M
CS
Fall to SCLK Setup Time
ns
t
CSS
DIN to SCLK Rise Setup Time
ns
t
DS
SCLK Clock Frequency
MHz
f
CLK
SCLK Pulse Width High
ns
t
CH
SCLK Pulse Width Low
ns
t
CL
SCLK to DOUT Valid
ns
t
DO
Note 7:
Guaranteed by design.
Note 8:
If
LDAC
is activated prior to
CS
's rising edge, it must stay low for t
LDW
or longer after
CS
goes high.
Note 9:
Minimum delay from 12th clock cycle to
CS
rise.
POWER SUPPLIES
SERIAL INTERFACE TIMING
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