參數(shù)資料
型號(hào): MAX510
廠商: Maxim Integrated Products, Inc.
英文描述: Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs(四通道,電壓輸出,串行,8位D/A轉(zhuǎn)換器)
中文描述: 四路、串行、8位DAC,滿擺幅輸出
文件頁數(shù): 10/20頁
文件大小: 306K
代理商: MAX510
M
Quad, S erial 8-Bit DACs
with Rail-to-Rail Outputs
10
______________________________________________________________________________________
t
LDW
SCLK
DIN
DOUT
LDAC
CS
t
DO
t
DH
t
DS
t
CSH0
t
CSS
t
CH
t
CL
t
CSH1
t
CSH2
t
CLL
NOTE:
TIMING SPECIFICATION t
CLL
IS RECOMMENDED TOMINIMIZE OUTPUT GLITCH, BUT IS NOT MANDATORY.
Figure 2. Detailed Serial Interface Timing (Mode 0 Shown)
Table 1. Serial-Interface Programming Commands
Mode 0, DOUT clocked out on falling edge of SCLK.
All DACs updated from input registers.
Mode 1, DOUT clocked out on rising edge of SCLK
(default). All DACs updated from respective input
registers.
LDAC
” Command, all DACs updated from respective
input registers.
12-Bit Serial Word
C1
0
0
0
0
0
0
1
1
X
0
0
1
1
C0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
1
1
A0
0
1
0
1
0
1
X
1
0
0
1
0
1
Function
LDAC
D7 . . . . . . . . D0
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
A1
X
X X X X X X X X
1
X
X X X X X X X X
1
X
X X X X X X X X
0
No Operation (NOP), shifts data in shift register.
X
X X X X X X X X
X
Update all DACs from shift register.
X
8-Bit DAC Data
Load input and DAC register A.
Load input and DAC register B.
Load input and DAC register C.
Load input and DAC register D.
1
1
1
1
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
Load DAC A input register, DAC output unchanged.
Load DAC B input register, DAC output unchanged.
Load DAC C input register, DAC output unchanged.
Load DAC D input register, DAC output unchanged.
1
1
1
1
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