參數(shù)資料
型號： MAX5019-MAX5020
廠商： Maxim Integrated Products, Inc.
英文描述： Current-Mode PWM Controllers with Integrated Startup Circuit
中文描述： 電流模式PWM集成啟動電路控制器
文件頁數(shù)： 12/14頁
文件大?。?/td> 328K
代理商： MAX5019-MAX5020
M
Choose MOSFETs with appropriate avalanche
power ratings.
5) Choose the tertiary winding turns ratio (N
T
/N
P
) so
that the minimum input voltage provides the mini-
mum operating voltage at V
DD
(13V). Use the follow-
ing equation to calculate the tertiary winding turns
ratio:
where:
V
DDMIN
is the minimum V
DD
supply voltage (13V).
V
DDMAX
is the maximum V
DD
supply voltage (36V).
V
IN_MIN
is the minimum input supply voltage (36V).
V
IN_MAX
is the maximum input supply voltage (72V
in this design example).
N
P
is the number of turns of the primary winding.
N
T
is the number of turns of the tertiary winding.
13 7
4
36
N
T
≤
≤
Choose N
T
= 6.
6) Choose R
SENSE
according to the following equation:
where:
V
ILim
is the current-sense comparator trip threshold
voltage (0.465V).
N
S
/N
P
is the secondary side turns ratio (5/14 in this
example).
I
OUTMAX
is the maximum DC output current (10A in
this example).
7) Choose the inductor value so that the peak ripple
current (LIR) in the inductor is between 10% and
20% of the maximum output current.
(
×
×
LIR
kHz I
2
275
where V
D
is the output Schottky diode forward volt-
age drop (0.5V).
8) The size and ESR of the output filter capacitor deter-
mine the output ripple. Choose a capacitor with a
low ESR to yield the required ripple voltage.
Use the following equations to calculate the peak-to-
peak output ripple:
where:
V
RIPPLE
is the combined RMS output ripple due to
V
RIPPLE,ESR
, the ESR ripple, and V
RIPPLE,C
, the
capacitive ripple. Calculate the ESR ripple and
capacitive ripple as follows:
V
RIPPLE,ESR
= I
RIPPLE
x ESR
V
RIPPLE,C
= I
RIPPLE
/(2 x
π
x 275kHz x C
OUT
)
Layout Recommendations
All connections carrying pulsed currents must be very
short, be as wide as possible, and have a ground plane
as a return path. The inductance of these connections
must be kept to a minimum due to the high di/dt of the
currents in high-frequency switching power converters.
Current loops must be analyzed in any layout pro-
posed, and the internal area kept to a minimum to
reduce radiated EMI. Ground planes must be kept as
intact as possible.
Chip Information
TRANSISTOR COUNT: 589
PROCESS: BiCMOS
V
V
V
RIPPLE
RIPPLEESR
RIPPLEC
=
+
,
,
2
2
L
-
≥
(
.
)
×
(
)
×
=
μ
5 5
.
1 0 198
.
kHz
0 4 275
10
4 01
.
A
H
L
V
-
OUT
≥
+
)
×
(
)
V
D
D
MIN
OUTMAX
1
R
SENSE
≤
×
=
0 465
.
5
14
1 2 10
.
109
V
m
R
V
N
N
SENSE
ILIM
×
S
P
≤
×
1 2
I
OUTMAX
36 7
72
14
5 33
.
7 14
.
.
.
1
N
T
×
≤
≤
×
V
V
N
N
V
V
N
DDMIN
IN_MIN
P
T
DDMAX
IN_MAX
P
+
×
≤
≤
+
×
0 7
.
0 7
.
V
7
1 + 14
14
DSMAX
≥
×
=
2
144
V
V
Current-Mode PWM Controllers with Integrated
Startup Circuit
12
______________________________________________________________________________________
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