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MAX4952
Quad Equalized 1.5/3.0/6.0GT/s
SAS/SATA Redriver
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Input Equalization (EQ0A, EQ1A,
EQ0B, EQ1B)
The MAX4952 features control logic inputs (EQ0A,
EQ1A, EQ0B, EQ1B) to enable input equalization on
each channel, providing 3dB of boost (see Note 4 in the
Electrical Characteristics table). Drive EQ_ high to
enable input equalization. Drive EQ_ low to disable input
equalization (see Table 3). EQ0A, EQ1A, EQ0B, and
EQ1B have internal pulldown resistors of 70k
Ω (typ).
Output Preemphasis (PE0A, PE1A,
PE0B, PE1B)
The MAX4952 features control logic inputs (PE0A,
PE1A, PE0B, PE1B) to enable output preemphasis on
either channel, providing 3dB of boost. The MAX4952
true preemphasis; the transition signal is increased
after a changing bit, thus increasing the total energy
content of the signal when employed. Drive PE_ high to
enable output preemphasis. Drive PE_ low to disable
output preemphasis (see Table 4). PE0A, PE1A, PE0B,
and PE1B have internal pulldown resistors of 70k
Ω (typ).
Applications Information
Exposed Pad Package
The exposed paddle, 42-pin TQFN package incorpo-
rates features that provide a very low thermal resistance
path for heat removal from the IC. The exposed paddle
on the MAX4952 must be soldered to GND for proper
thermal and electrical performance. For more informa-
tion on exposed paddle packages, refer to Maxim
Application Note HFAN-08.1:
Thermal Considerations of
QFN and Other Exposed-Paddle Packages.
Layout
Use controlled-impedance transmission lines to inter-
face with high-speed inputs and outputs of the
MAX4952. Place 2.2F and 0.01F power-supply
bypass capacitors as close as possible to VCC, recom-
mended on each VCC pin.
Power-Supply Sequencing
Caution: Do not exceed the absolute maximum rat-
ings because stresses beyond the listed ratings
may cause permanent damage to the device.
Proper power-supply sequencing is recommended for
all devices. Always apply VCC before applying signals,
especially if the signal is not current limited.
Chip Information
PROCESS: BiCMOS
EQ1_
EQ0_
CHANNEL 1_
(dB)
CHANNEL 0_
(dB)
00
0
1
0
3 (typ)
1
0
3 (typ)
0
1
3 (typ)
Table 3. Input Equalization (EQ0_, EQ1_)
PE1_
PE0_
CHANNEL 1_
(dB)
CHANNEL 0_
(dB)
00
0
1
0
3 (typ)
1
0
3 (typ)
0
1
3 (typ)
Table 4. Output Preemphasis (PE0_, PE1_)
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
42 TQFN-EP
T423590M-1