resistance (RON
參數(shù)資料
型號(hào): MAX4717EUB+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 2/16頁(yè)
文件大小: 0K
描述: IC SWITCH SPDT 10UMAX
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
功能: 開關(guān)
電路: 2 x SPDT
導(dǎo)通狀態(tài)電阻: 4.5 歐姆
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 1.8 V ~ 5.5 V
電流 - 電源: 1µA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-µMAX
包裝: 帶卷 (TR)
MAX4717/MAX4718
Detailed Description
The MAX4717/MAX4718 high-speed, low-voltage, low on-
resistance (RON), dual SPDT analog switches operate
from a single +1.8V to +5.5V supply. The switches feature
break-before-make switching operation and fast switch-
ing speeds (tON = 80ns (max), tOFF = 40ns (max)).
These switches have low 15pF on-channel capaci-
tance, which allows for 12Mbps switching of the data
signals for USB 1.0/1.1 applications. The MAX4717 is
designed to switch D+ and D- USB signals with a guar-
anteed skew of less than 2ns (see Figure 4) as mea-
sured from 50% of the input signal to 50% of the output
signal.
Applications Information
Digital Control Inputs
The MAX4717/MAX4718 logic inputs accept up to
+5.5V regardless of supply voltage. For example, with
a +3.3V supply, IN_ can be driven low to GND and high
to +5.5V allowing for mixing of logic levels in a system.
Driving the control logic inputs rail-to-rail minimizes
power consumption. For a +3V supply voltage, the
logic thresholds are 0.5V (low) and 1.4V (high); for a
+5V supply voltage, the logic thresholds are 0.8V (low)
and 2.0V (high).
Analog Signal Levels
The on-resistance of the MAX4717/MAX4718 changes
very little for analog input signals across the entire supply
voltage range (see the Typical Operating Characteristics).
The switches are bidirectional, so the NO_, NC_, and
COM_ pins can be either inputs or outputs.
Power-Supply Sequencing and
Overvoltage Protection
Caution: Do not exceed the absolute maximum rat-
ings because stresses beyond the listed ratings
may cause permanent damage to the device.
Proper power-supply sequencing is recommended for
all CMOS devices. Always apply V+ before applying
analog signals, especially if the analog signal is not
current-limited.
UCSP Application Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, printed circuit
board techniques, bump-pad layout, and recommend-
ed reflow temperature profile as well as the latest infor-
mation on reliability testing results, go to the Maxim
web site at www.maxim-ic.com/ucsp to find the
Application Note: USCP—A Wafer-Level Chip-Scale
Package.
Chip Information
TRANSISTOR COUNT: 235
PROCESS: BiCMOS
4.5
/20, 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
10
______________________________________________________________________________________
PIN
UCSP
MAX/
TDFN
NAME
FUNCTION
A1
7
NC2
Analog Switch 2—Normally Closed
Terminal
A2
8
IN2
Analog Switch 2—Digital Control
Input
A3
9
COM2
Analog Switch 2—Common
Terminal
A4
10
NO2
Analog Switch 2—Normally Open
Terminal
B1
6
GND
Ground. Connection.
B4
1
V+
Positive-Supply Voltage
C1
5
NC1
Analog Switch 1—Normally Closed
Terminal
C2
4
IN1
Analog Switch 1—Digital Control
Input
C3
3
COM1
Analog Switch 1—Common
Terminal
C4
2
NO1
Analog Switch 1—Normally Open
Terminal
——
EP
Exposed Pad (for TDFN package
only). Connect to ground.
Pin Description
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