參數(shù)資料
型號(hào): MAX4688EBT+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 6/8頁(yè)
文件大?。?/td> 0K
描述: IC SWITCH SPDT 6UCSP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
功能: 開關(guān)
電路: 1 x SPDT
導(dǎo)通狀態(tài)電阻: 2.5 歐姆
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 1.8 V ~ 5.5 V
電流 - 電源: 1µA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 6-WFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 6-uCSP(1.57x1.16)
包裝: 帶卷 (TR)
Proper power-supply sequencing is recommended for all
CMOS devices. Always apply V+ before applying analog
signals, especially if the analog signal is not current limit-
ed. If this sequencing is not possible, and if the analog
inputs are not current limited to <20mA, add a small-sig-
nal diode (D1) as shown in Figure 1. Adding a protection
diode reduces the analog range to a diode drop (about
0.7V) below V+ (for D1). RON increases slightly at low
supply voltages. Maximum supply voltage (V+) must not
exceed +6V.Protection diode D1 also protects against
some overvoltage situations. No damage will result on
Figure 1’s circuit if the supply voltage is below the
absolute maximum rating and if a fault voltage up to the
absolute maximum rating is applied to an analog signal
pin.
UCSP Package Consideration
For general UCSP package information and PC layout
considerations, please refer to the Maxim Application
Note (Wafer-Level Ultra-Chip-Board-Scale Package).
UCSP Reliability
The chip-scale package (UCSP) represents a unique
packaging form factor that may not perform equally to a
packaged product through traditional mechanical relia-
bility tests. CSP reliability is integrally linked to the user’s
assembly methods, circuit board material, and usage
environment. The user should closely review these areas
when considering use of a CSP package. Performance
through Operating Life Test and Moisture Resistance
remains uncompromised as it is primarily determined by
the wafer-fabrication process.
Mechanical stress performance is a greater considera-
tion for a CSP package. CSPs are attached through
direct solder contact to the user’s PC board, foregoing
the inherent stress relief of a packaged product lead
frame. Solder joint contact integrity must be considered.
Information on Maxim’s qualification plan, test data, and
recommendations are detailed in the UCSP application
note, which can be found on Maxim’s website at
www.maxim-ic.com.
MAX4686/MAX4687/MAX4688
2.5
, Low-Voltage, SPST/SPDT
Analog Switches in UCSP Package
6
_______________________________________________________________________________________
Test Circuits/Timing Diagrams
tr < 5ns
tf < 5ns
50%
0
LOGIC
INPUT
RL
50
COM_
GND
IN_
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
VOUT = VN_
(
RL
)
RL + RON
VIN_
V+
tOFF
0
NO_
OR NC
0.9 x V0UT
0.9 x VOUT
tON
VOUT
SWITCH
OUTPUT
LOGIC
INPUT
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
V+
CL
35pF
V+
VOUT
MAX4686
MAX4687
MAX4688
50%
V+
0
LOGIC
INPUT
VOUT
0.9 x VOUT
tD
LOGIC
INPUT
RL
300
GND
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_
IN_
NC_
VOUT
V+
CL
35pF
VN_
COM_
MAX4688
tr < 5ns
tf < 5ns
Figure 2. Switching Time
Figure 3. Break-Before-Make Interval (MAX4688 only)
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