參數(shù)資料
型號(hào): MAX4356ECD
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): 運(yùn)動(dòng)控制電子
英文描述: 16x16 Nonblocking Video Crosspoint Switch with On-Screen Display Insertion and I/O Buffers
中文描述: 16-CHANNEL, CROSS POINT SWITCH, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, TQFP-128
文件頁(yè)數(shù): 11/41頁(yè)
文件大小: 853K
代理商: MAX4356ECD
M
16 x 16 Nonbloc king Video Crosspoint S witc h
with On-S c reen Display Insertion and I/O Buffers
______________________________________________________________________________________
11
SWITCHING CHARACTERISTICS
((V
CC
- V
EE
) = +4.5V to +10.5V, V
DD
= +2.7V to +5.5V, DGND = AGND = 0, V
IN
_ = V
OSDFILL
_ = 0 for dual supplies, V
IN
_ =
V
OSDFILL
_ = +1.75V for single supply, R
L
= 150
to AGND, CL= 100pF, A
V
= +1V/V, and T
A
= T
MIN
to T
MAX
, unless otherwise
noted. Typical values are at T
A
= +25
°
C. )
PARAMETER
SYMBOL
CONDITIONS
Delay:
UPDATE
to Video Out
t
PdUdVo
V
IN
= 0.5V step
MODE = 0, time to
AOUT
= low after
UPDATE
= low
t
PdOkVo/
t
PdOfVo
Logic state change in DOUT on active
SCLK edge
Delay: Output Disable
t
PdHOe
V
OUT
= 0.5V, 1k
pulldown to AGND
Output disabled, 1k
pulldown to AGND,
V
IN
= 0.5V
Setup:
CE
to SCLK
t
SuCe
Setup: DIN to SCLK
t
SuDi
Hold Time: SCLK to DIN
t
HdDi
Minimum High Time: SCLK
t
MnHCk
Minimum Low Time: SCLK
t
MnLCk
Minimum Low Time:
UPDATE
t
MnLUd
Rising edge of
UPDATE
to falling edge of
SCLK
Falling edge of SCLK to falling edge of
UPDATE
Minimum time from clock edge to MODE
with valid data clocking
Minimum time from clock edge to MODE
with valid data clocking
Minimum Low Time:
RESET
t
MnLRst
Delay:
RESET
t
PdRst
10k
pulldown to AGND, 0.5V step
MIN
TYP
200
MAX
450
UNITS
ns
Delay:
UPDATE
to
AOUT
t
PdUdAo
30
200
ns
V
DD
= +5V
V
DD
= +3V
40
60
Delay: OSDKEY_ to Output
V
OUT
= 0.5V step
ns
Delay: SCLK to DOUT Valid
t
PdDo
30
200
ns
300
800
ns
Delay: Output Enable
t
PdLOe
200
800
ns
100
ns
ns
ns
ns
ns
ns
100
100
100
100
100
Setup Time:
UPDATE
to SCLK
t
SuHUd
100
ns
Hold Time: SCLK to
UPDATE
t
HdHUd
100
ns
Setup Time: MODE to SCLK
t
SuMd
100
ns
Hold Time: MODE to SCLK
t
HdMd
100
ns
300
600
ns
ns
Note 1:
Associated output voltage may be determined by multiplying the input voltage by the specified gain (A
V
) and adding output
offset voltage. Gain is specified for IN_ and OSDFILL_ signal paths.
Note 2:
Logic-level characteristics apply to the following pins: DIN, DOUT, SCLK,
CE
,
UPDATE
,
RESET
, A3
A0, MODE,
AOUT
, and
OSDKEY_.
Note 3:
Switching transient settling time is guaranteed by the settling time (t
S
) specification. Switching transient is a result of updat-
ing the switch matrix.
Note 4:
Input test signal: 3.58MHz sine wave of amplitude 40IRE superimposed on a linear ramp (0 to 100IRE). IRE is a unit of
video-signal amplitude developed by the International Radio Engineers: 140IRE = 1.0V.
Note 5:
All devices are 100% production tested at T
A
= +25
°
C. Specifications over temperature limits are guaranteed by design.
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