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參數(shù)資料
| 型號(hào)： | MAX3992UTG+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DATA RECOVERY W/EQ 24-TQFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR） |
| PLL： | 是 |
| 主要目的： | SONET/SDH.XFP 光學(xué)接收器 |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 693.5MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-TQFN-EP（4x4） |
| 包裝： | 帶卷 (TR) |
MAX3992
Applications Information
Exposed Pad (EP) Package
The exposed pad, 24-pin QFN incorporates features
that provide a very low thermal-resistance path for heat
removal from the IC. The pad is electrical ground on the
MAX3992 and must be soldered to the circuit board for
proper thermal and electrical performance.
Layout Considerations
For best performance, use good high-frequency layout
techniques. Filter voltage supplies, keep ground con-
nections short, and use multiple vias where possible.
Use controlled-impedance transmission lines to inter-
face with the MAX3992 high-speed inputs and outputs.
Power-supply decoupling should be placed as close to
VCC as possible. To reduce feedthrough, take care to
isolate the input signals from the output signals.
10Gbps Clock and Data Recovery
with Equalizer
10
______________________________________________________________________________________
Table 3. Functional Control
FCTL1
FCTL2
DESCRIPTION
00
Normal operation, serial clock output
disabled.
1
0
Standby power-down mode.
01
Normal operation, serial clock output
disabled.
11
Serial clock output enabled for jitter
testing.
Figure 5. CML Input Model
SDI+
SDI-
VCC
50
Figure 6. CML Output Model
VCC
GND
SDO+
SDO-
50
Figure 7. Polarity (POL) Function
(SDI+) - (SDI-)
(SDO+) - (SDO-)
POL = VCC
(SDO+) - (SDO-)
POL = GND
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