參數(shù)資料
型號: MAX3969
廠商: Maxim Integrated Products, Inc.
英文描述: 2x2 Crosspoint Switch : LVDS Outputs 16-SOIC -40 to 85
中文描述: 200Mbps SFP限幅放大器
文件頁數(shù): 4/11頁
文件大?。?/td> 724K
代理商: MAX3969
M
200Mbps SFP Limiting Amplifier
4
_______________________________________________________________________________________
10
μ
s/div
POWER-DETECT TIMING WITH SQUELCH
(INPUT = 12mV
P-P
, C
FILTER
= 0.01
μ
F,
R2 = 15k
, 155Mbps, 2
23
- 1 PRBS)
IN
OUT
LOS
SD
PULSE-WIDTH DISTORTION
vs. DIFFERENTIAL INPUT VOLTAGE
M
DIFFERENTIAL INPUT VOLTAGE (mV
P-P
)
P
1000
100
10
10
20
30
40
50
60
70
80
90
100
0
1
10,000
100Mbps
1-0 PATTERN
INPUT DATA THROUGH
117MHz FILTER
UNFILTERED
INPUT DATA
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
-40
-15
AMBIENT TEMPERATURE (
°
C)
10
35
60
85
DATA OUTPUT TRANSITION TIME
vs. TEMPERATURE
M
T
Typical Operating Characteristics (continued)
(V
CC
= +3.3V, PECL outputs terminated with 50
to V
CC
- 2V, R1 = 100k
, T
A
= +25°C, unless otherwise noted.)
Pin Description
PIN
NAME
FUNCTION
1
INV
Inverting Input of Internal Op Amp that Sets Power-Detect Threshold Voltage (Figure 1). Connect a
resistor from V
TH
to INV (R2), and from INV to ground (R1 = 100k
), to program the desired threshold
voltage.
2
FILTER
Filter Output of Logarithmic Full-Wave Detectors (FWDs). The FWD outputs are summed together at
FILTER to generate the RSSI output. Connect a capacitor from FILTER to V
CC
for proper operation.
3
RSSI
Received-Signal-Strength Indicator Output. The voltage at RSSI indicates the input-signal power. The
RSSI output is reduced approximately 120mV when LOS is asserted.
4
5
IN-
IN+
GND
CZP
CZN
V
CCO
OUT+
OUT-
Inverting Data Input
Noninverting Data Input
Ground
Autozero Capacitor Input. Connect a 0.027μF capacitor between CZP and CZN.
Autozero Capacitor Input. Connect a 0.027μF capacitor between CZP and CZN.
Output-Buffer Supply Voltage. Connect to the same potential as V
CC
.
Noninverting PECL Data Output. Terminate with 50
to (V
CC
- 2V).
Inverting PECL Data Output. Terminate with 50
to (V
CC
- 2V).
6 , 7, 8
9
10
11
12
13
14
SD
Signal Detect, PECL Output. The SD output is high when input power is above the power-detect
threshold, and low when input power is below the power-detect threshold. This pin is PECL-
compatible and should be terminated with 50
to (V
CC
- 2V) or equivalent.
15
LOS
Loss-of-Signal Output, TTL Open Collector (with ESD Protection). The LOS output is high when input
power is below the power-detect threshold, and low when input power is above the power-detect
threshold.
16
LOS
Inverted Loss-of-Signal Output, TTL Open Collector (with ESD Protection). The
LOS
output is low
when input power is below the power-detect threshold, and high when input power is above the
power-detect threshold.
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