參數(shù)資料
型號： MAX3941
廠商： Maxim Integrated Products, Inc.
英文描述： 10Gbps EAM Driver with Integrated Bias Network
中文描述： 10Gbps EAM驅動器，帶有偏置網絡
文件頁數(shù)： 3/11頁
文件大小： 319K
代理商： MAX3941
M
10Gbps EAM Driver with Integrated
Bias Network
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
EE
= -5.5V to -4.9V, T
A
= -40
°
C to +85
°
C. Typical values are at V
EE
= -5.2V, I
BIAS
= 30mA, I
MOD
= 100mA, and T
A
= +25
°
C, unless
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Modulation Set Bandwidth
Modulation depth 10%, 50
driver load,
Figure 2
5
MHz
MODSET Input Resistance
20
k
Modulation-Current Temperature
Stability
(Note 6)
-957
0
ppm/
°
C
Modulation-Current-Setting Error
Output Resistance
50
driver load, T
A
= +25
°
C
OUT to GND
-10
42.5
+10
58.5
%
R
OUT
50
Total Off Current
BIASSET = V
EE
,
MODEN
= V
EE
, MODSET =
V
EE
, DATA+ = high, DATA- = low
1.2
mA
Output Return Loss
RL
OUT
I
BIAS
= 30mA,
I
MOD
= 50mA
20% to 80% (Notes 6, 8)
Figure 3 (Note 6)
(Notes 6, 8)
≤
15GHz
10
dB
Output Edge Speed
Setup/Hold Time
Pulse-Width Adjustment Range
23
32
ps
ps
ps
t
SU
, t
HD
25
±30
±50
Pulse-Width Control Input Range
(Single Ended)
For PWC+ and PWC-
V
EE
+
0.5
V
EE
+
1.5
V
Pulse-Width Control Input Range
(Differential)
(PWC+) - (PWC-)
-0.5
+0.5
V
Output Overshoot
Driver Random Jitter
Driver Deterministic Jitter
CONTROL INPUTS
δ
(Notes 6, 8)
(Note 6)
PWC- = GND (Notes 6, 9)
10
0.3
6.8
%
RJ
DR
DJ
DR
0.7
11
ps
RMS
ps
P-P
Input High Voltage
V
IH
(Note 10)
V
EE
+
2.0
V
Input Low Voltage
V
IL
(Note 10)
V
EE
+
0.8
V
Input Current
(Note 10)
-80
+200
μA
Note 1:
Supply current remains elevated once the retiming function is enabled. Power must be cycled to reduce supply
current after the retiming function is disabled.
Note 2:
Power-supply noise rejection is specified as PSNR = 20log(V
noise (on Vcc)
/
V
OUT
). V
OUT
is the voltage across a 50
load.
V
noise (on Vcc)
= 100mV
P-P
.
Note 3:
For DATA+, DATA-, CLK+, and CLK-.
Note 4:
CLK input characterized at 10.7Gbps.
Note 5:
R
BSEQV
= (V
BIASSET
- V
EE
) / I
BIAS
with
MODEN
= V
EE
, DATA+ = high, and DATA- = low.
Note 6:
Guaranteed by design and characterization using the circuit shown in Figure 4.
Note 7:
R
MODEQV
= (V
MODSET
- V
EE
) / (I
MOD
- 37mA) with BIASSET = V
EE
.
Note 8:
50
load, characterized at 10.7Gbps with a 1111 1111 0000 0000 pattern.
Note 9:
Deterministic jitter is defined as the arithmetic sum of pulse-width distortion (PWD) and pattern-dependent jitter (PDJ).
Measured with a 10.7Gbps 2
7
- 1 PRBS pattern with eighty 0s and eighty 1s inserted in the data pattern.
Note 10:
For
MODEN
and PLRT.
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