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參數(shù)資料
| 型號(hào)： | MAX3876EHJ |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 2.5Gbps, Low-Power, #.3V Clock Recovery and Data Retiming IC |
| 中文描述： | CLOCK RECOVERY CIRCUIT, PQFP32 |
| 封裝： | 5 X 5 MM, 1 MM HEIGHT, TQFP-32 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 744K |
| 代理商： | MAX3876EHJ |
M
2.5Gbps, Low-Power, +3.3V
Clock Recovery and Data Retiming IC
_______________________________________________________________________________________
5
SDI+
SDI-
SLBI+
SLBI-
SCLKO-
SCLKO+
SDO+
SDO-
PHASE AND
FREQUENCY
DETECTOR
FIL+
FIL-
LOOP
FILTER
MAX3876
LOL
SIS
MUX
AMP
AMP
CK
D
Q
VCO
I
Q
CML
CML
TTL
Figure 3. Functional Diagram
NAME
SCLKO+
FUNCTION
PIN
19
25
30
31
LOL
FIL-
FIL+
Loss-of-Lock Output, TTL, PLL loss-of-lock monitor, active low (internal 10k
pull-up resistor)
Negative Filter Input. PLL loop filter connection. Connect a 1.0μF capacitor between FIL+ and FIL-.
Positive Filter Input. PLL loop filter connection. Connect a 1.0μF capacitor between FIL+ and FIL-.
23
SDO+
Positive Data Output, CML, 2.488Gbps
22
SDO-
Negative Data Output, CML, 2.488Gbps
Positive Serial Clock Output, CML, 2.488GHz. SDO+ is clocked out on the rising edge of SCLKO+.
Pin Description (continued)
Detailed Description
The MAX3876 consists of a fully integrated phase-
locked loop (PLL), input amplifier, data retiming block,
and CML output buffer (Figure 3). The PLL consists of
a phase/frequency detector (PFD), a loop filter, and a
voltage-controlled oscillator (VCO).
This device is designed to deliver the best combination
of jitter performance and power dissipation by using a
fully differential signal architecture and low-noise
design techniques.
Input Amplifier
Input amplifiers are implemented for both the main data
and system loopback inputs. These amplifiers accept
DC-coupled differential input amplitudes from 50mVp-p
up to 1000mVp-p. With AC-coupling, differential input
signal amplitudes can be increased to a maximum of
1600mVp-p. The bit error rate is better than 1
·
10
-10
for
input signals as small as 10mVp-p, though the jitter tol-
erance performance will be degraded. For interfacing
with PECL signal levels, see
Applications Information
.
Phase Detector
The phase detector incorporated in the MAX3876 pro-
duces a voltage proportional to the phase difference
between the incoming data and the internal clock.
Because of its feedback nature, the PLL drives the
error voltage to zero, aligning the recovered clock to
the center of the incoming data eye for retiming.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX3876EHJ+ | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Integrated Circuits (ICs) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3876EHJ+T | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Integrated Circuits (ICs) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3876EHJ-T | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX3876EVKIT | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| MAX3877E/D | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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