參數(shù)資料
型號: MAX3875EHJ
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 數(shù)字傳輸電路
英文描述: 2.5Gbps, Low-Power, #.3V Clock Recovery and Data Retiming IC
中文描述: CLOCK RECOVERY CIRCUIT, PQFP32
封裝: 5 X 5 MM, 1 MM HEIGHT, EXPOSED PAD, TQFP-32
文件頁數(shù): 6/8頁
文件大小: 126K
代理商: MAX3875EHJ
Frequenc y Detec tor
The digital frequency detector (FD) aids frequency
acquisition during start-up conditions. The frequency
difference between the received data and the VCO
clock is derived by sampling the in-phase and quadra-
ture VCO outputs on both edges of the data input sig-
nal. Depending on the polarity of the frequency
difference, the FD drives the VCO until the frequency
difference is reduced to zero. Once frequency acquisi-
tion is complete, the FD returns to a neutral state. False
locking is completely eliminated by this digital frequen-
cy detector.
Loop Filter and V CO
The phase detector and frequency detector outputs are
summed into the loop filter. An external capacitor, C
F
,
is required to set the PLL damping ratio. Refer to
Design Procedure for guidelines on selecting this
capacitor.
The loop filter output controls the on-chip LC VCO run-
ning at 2.488GHz. The VCO provides low phase noise
and is trimmed to the correct frequency. Clock jitter
generation is typically 1.2ps
RMS
within a jitter band-
width of 12kHz to 20MHz.
Loss-of-Loc k Monitor
A loss-of-lock (
LOL
) monitor is incorporated in the
MAX3875 frequency detector. A loss-of-lock condition
is signaled immediately with a TTL low. When the PLL is
frequency locked,
LOL
switches to TTL high in approxi-
mately 800ns.
Note that the
LOL
monitor is only valid when a data
stream is present on the inputs to the MAX3875. As a
result,
LOL
does not detect a loss-of-power condition
resulting from a loss of the incoming signal.
Design Proc edure
S etting the Loop Filter
The MAX3875 is designed for both regenerator and
receiver applications. Its fully integrated PLL is a clas-
sic second-order feedback system, with a loop band-
width (f
L
) fixed at 1.1MHz. The external capacitor, C
F
,
can be adjusted to set the loop damping. Figures 4 and
5 show the open-loop and closed-loop transfer func-
tions.
The PLL zero frequency, f
Z
, is a function of external
capacitor C
F
, and can be approximated according to:
For an overdamped system (f
Z
/f
L
) < 0.25, the jitter peak-
ing (M
P
) of a second-order system can be approxi-
mated by:
For example, using C
F
= 0.1μF results in a jitter peaking
of 0.2dB. Reducing C
F
below 0.01μF may result in PLL
instability. The recommended value for C
F
= 1.0μF to
guarantee a maximum jitter peaking of less than 0.1dB.
C
F
must be a low TC, high-quality capacitor of type
X7R or better.
M
f
f
P
Z
L
=
20log 1+
f
( )
z
F
=
1
2
π
M
2.5Gbps, Low-Power, +3.3V
Cloc k Rec overy and Data Retiming IC
6
_______________________________________________________________________________________
C
F
= 1.0
μ
F
f
Z
= 2.6kHz
C
F
= 0.1
μ
F
f
Z
= 26kHz
H
O
(j2
π
f) (dB)
O
1000
f (kHz)
100
10
1
Figure 4. Open-Loop Transfer Function
C
F
= 1.0
μ
F
H(j2
π
f) (dB)
1000
100
10
1
f (kHz)
-3
0
C
C
F
= 0.1
μ
F
Figure 5. Closed-Loop Transfer Function
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