參數(shù)資料
型號(hào): MAX3873A
廠(chǎng)商: Maxim Integrated Products, Inc.
英文描述: 16-Channel LVDM Transceiver 64-TSSOP -40 to 85
中文描述: 低功耗、結(jié)構(gòu)緊湊的2.5Gbps/2.7Gbps時(shí)鐘恢復(fù)與數(shù)據(jù)再定時(shí)IC
文件頁(yè)數(shù): 4/12頁(yè)
文件大?。?/td> 793K
代理商: MAX3873A
M
Low-Power, Compact 2.5Gbps or 2.7Gbps
Clock-Recovery and Data-Retiming IC
4
_______________________________________________________________________________________
Figure 1. Definition of Input Voltage Swing
Figure 2. Definition of Clock-to-Q Delay
(a) AC-COUPLED SINGLE-ENDED INPUT (CML OR PECL)
(b) DC-COUPLED SINGLE-ENDED CML INPUT
25mV
25mV
800mV
800mV
V
CC
+ 0.4V
V
CC
V
CC
- 0.4V
V
CC
V
CC
- 0.4V
V
CC
- 0.8V
SCLKO+
SDO
t
CLK
t
CLK-Q
Figure 4. Definition of
LOL
Assert Time and Frequency Acquisition Time
INPUT DATA
FREQUENCY ACQUISITION TIME
LOL OUTPUT
LOL ASSERT TIME
Figure 3. Definition of Phase Acquisition Time
SERIAL DATA
1200 BITS OF 1–0 PATTERN
<2
μ
s
FASTRACK
DATA
VCO CLOCK PHASE ALIGNED TO INPUT DATA
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 3.0V to 3.6V, C
F
= 0.022μF, T
A
= -40°C to +85°C. Typical values are at V
CC
= 3.3V, 2.488Gbps, T
A
= +25°C, unless otherwise
noted.) (Note 4)
Note 1:
At T
A
= -40°C, DC characteristics are guaranteed by design and characterization.
Note 2:
CML outputs open.
Note 3:
R
L
= 50
to V
CC
.
Note 4:
AC characteristics are guaranteed by design and characterization.
Note 5:
Relative to the falling edge of SCLKO+. See Figure 2.
Note 6:
Measured with 2
23
- 1 PRBS.
Note 7:
Jitter BW = 12kHz to 20MHz.
Note 8:
RATESET = low.
Note 9:
RATESET = high.
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