參數(shù)資料
型號: MAX3740A
廠商: Maxim Integrated Products, Inc.
英文描述: Full-Duplex LVDM Transceiver 8-MSOP -40 to 85
中文描述: 3.2Gbps、SFP VCSEL驅(qū)動器,帶有診斷監(jiān)視器
文件頁數(shù): 4/14頁
文件大小: 286K
代理商: MAX3740A
M
3.2Gbps S FP V CS EL Driver with Diagnostic
Monitors
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +2.97V to +3.63V, T
A
= -40
°
C to +85
°
C. Typical values are at V
CC
= +3.3V, TC1 and TC2 are shorted, PEAKSET open, T
A
=
+25
°
C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SAFETY FEATURES
(see the
Typical Operating Characteristics
section)
High-Current Fault Threshold
V
BIAS
Fault Threshold
Power-Monitor Fault Threshold
V
BMTH
V
BTH
V
PMTH
V
BIASMON
> V
BMTH
causes a fault
V
BIAS
referenced to V
CC
V
PWRMON
> V
PMTH
causes a fault
0.7
0.8
-0.2
0.8
0.9
V
V
V
-0.250
0.7
-0.150
0.9
TX Disable Time
t_
OFF
Time from rising edge of TX_DISABLE to
I
BIAS
= I
BIAS_OFF
and I
MOD
= I
MOD_OFF
(Note 6)
1.8
5
μs
TX Disable Negate Time
t_
ON
Time from rising edge of TX_DISABLE to
I
BIAS
and I
MOD
at 99% of steady state
(Note 6)
55
500
μs
Fault Reset Time
t_
INIT
1
Time to set V
FAULT
= low after power-on or
after rising edge of TX_DISABLE (Note 6)
60
200
ms
Power-On Time
t_
INIT
2
Time after power-on to transmitter-on with
TX_DISABLE low (Note 6)
60
200
ms
Fault Assert Time
t_
FAULT
Time from fault occurrence to V
FAULT
=
high; C
FAULT
< 20pF, R
FAULT
= 4.7k
(Note 6)
1.4
50
μs
Fault Delay Time
t_
FLTDLY
Time from fault to I
BIAS
= I
BIAS_OFF
and
I
MOD
= I
MOD_OFF
(Note 6)
1
5
μs
TX_DISABLE Reset
t_
RESET
Time TX_DISABLE must be held high to
reset FAULT (Note 6)
1
μs
Note 1:
Supply current measurements exclude I
BIAS
from the total current.
Note 2:
Tested with R
PEAK
= 1.18k
.
Note 3:
Measured by applying a pattern that contains 20μs of K28.5, followed by 5μs of zeros, then 20μs of K28.5, followed by 5μs
of ones. Data rate is equal to 2.5Gbps, with inputs filtered using 1.8GHz Bessel filters.
Note 4:
V
BIAS
< V
CC
- 0.7V.
Note 5:
Variation of bias monitor gain for any single part over the range of V
CC
, temperature, 3mA < I
BIAS
< 15mA.
Note 6:
Guaranteed by design and characterization.
Note 7:
Measured electrically with a 50
load AC-coupled to OUT+.
Note 8:
Deterministic jitter is the peak-to-peak deviation from the ideal time crossings measured with a K28.5 bit pattern at 3.2Gbps
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