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參數(shù)資料
| 型號(hào)： | MAX3693EVKIT |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Low-Power.Quad.10-Bit Voltage-Output DAC with Serial Interface[MAX5250/MAX5250ACAP/MAX5250ACAP-T/MAX5250ACPP/MAX5250AEAP/MAX5250AEAP-T/MAX5250AEPP/MAX5250BCAP/MAX5250BCAP-T/MAX5250BCPP/MAX5250BEAP/MAX5250BEAP-T/MAX5250BEPP/MAX5250BMJP ] |
| 中文描述： | MAX3693評(píng)估板 |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大小： | 327K |
| 代理商： | MAX3693EVKIT |
M
3.3V, 622Mbps LVDS,
Dual 4:2 Crosspoint Switch
_______________________________________________________________________________________
3
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to 3.6V, LVDS differential load = 100
±1%, T
A
= 0
°
C to +85
°
C. Typical values are at V
CC
= +3.3V, T
A
= +25
°
C,
unless otherwise noted.) (Note 1)
Note 1:
AC characteristics are guaranteed by design and characterization.
Note 2:
Deterministic jitter (DJ) is the arithmetic sum of pattern-dependent jitter and pulse-width distortion. DJ is measured while
applying 100mVp-p noise (f
≤
2MHz) to the power supply.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
622
240
2.8
42
24
MAX
UNITS
Mbps
ps
ps
RMS
ps
ps
Parallel Input/Output Data Rate
Output Rise/Fall Time
Output Random Jitter
Output Deterministic Jitter
LVDS Output Differential Skew
t
r
, t
f
RJ
DJ
t
SKEW1
20% to 80%
150
350
4
200
50
(Note 2)
LVDS Output Channel-to-
Channel Skew
t
SKEW2
110
ps
LVDS Output Enable Time
LVDS Output Disable Time
LVDS Propagation Delay from
Input to Output
266
66
ns
ns
t
D
2.5
ns
Figure 1. LVDS Output Levels
LVDS+
SINGLE ENDED
125mV MIN
200mV MAX
125mV MIN
200mV MAX
250mV MIN
400mV MAX
500mV MIN
800mV MAX
250mV MIN
400mV MAX
250mV MIN
400mV MAX
LVDS-
SINGLE ENDED
(LVDS+) - (LVDS-)
DIFFERENTIAL OUTPUT
VOLTAGE
V
OS
= 1.2V ±75mV
V
OS
= 1.2V ±75mV
0
V
OD
V
OH
V
OL
V
OH
V
OL
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