參數(shù)資料
型號(hào): MAX3676EHJ
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 2/15頁(yè)
文件大小: 0K
描述: IC RECOV/RETIME 622MBPS 32-TQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 360
類(lèi)型: 時(shí)鐘和數(shù)據(jù)恢復(fù)(CDR),多路復(fù)用器
PLL:
主要目的: SONET/SDH
輸入: PECL
輸出: PECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-TQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(5x5)
包裝: 托盤(pán)
MAX3676
622Mbps, 3.3V Clock-Recovery and
Data-Retiming IC with Limiting Amplifier
10
______________________________________________________________________________________
Note that the LOL monitor is only valid when a data
stream is present on the inputs to the MAX3676. As a
result, LOL does not detect a loss-of-power condition
resulting from a loss of the incoming signal. See the
Loss-of-Power Monitor section for this type of indicator.
Input and Output Terminations
The MAX3676 digital data and clock I/Os (DDI+, DDI-,
SDO+, SDO-, SCLK+, and SCLK-) are designed to
interface with PECL signal levels. It is important to bias
these ports appropriately. A circuit that provides a
Thevenin equivalent of 50
Ω to VCC - 2V should be used
with fixed-impedance transmission lines for proper ter-
mination. Make sure that the differential outputs have
balanced loads.
The digital data input signals (DDI+ and DDI-) are dif-
ferential inputs to an emitter-coupled pair. As a result,
the MAX3676 can accept differential input signals as
low as 250mV. These inputs can also be driven single-
ended by externally biasing DDI- to the center of the
voltage swing.
The MAX3676’s performance can be greatly affected
by circuit board layout and design. Use good high-fre-
quency design techniques, including minimizing
ground inductance and using fixed-impedance trans-
mission lines on the data and clock signals. Power-sup-
ply decoupling should be placed as close to VCC as
possible. Take care to isolate the input from the output
signals to reduce feedthrough.
Applications Information
Driving the Limiting Amplifier
Single-Ended
There are three important requirements for driving the
limiting amplifier from a single-ended source (Figure 5):
1) There must be no DC-coupling to the ADI+ and ADI-
inputs. DC levels at these inputs disrupt the offset-
correction loop.
2) The terminating resistor RT (50
Ω) must be referenced
to the ADI- input to minimize common-mode coupling
problems.
3) The low-frequency cutoff for the limiting amplifier
is determined by either CIN and the 2.5k
Ω input
impedance or Cb/2 together with RT. With Cb = 0.22μF
and RT = 50
Ω,the low-frequency cutoff is 29kHz.
ACQUIRE
NO DATA
LOP
OUTPUT
LEVEL
LOCKED
TIME
LOL
Figure 4. Loss-of-Lock Output
CIN
5.6nF
Cb
0.22
μF
Cb
0.22
μF
RT
50
Ω
2.5k
Ω
ADI+
ADI-
MAX3676
Figure 5. Single-Ended Input Termination
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MAX3676EHJ+ 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 622Mbps 3.3V Clock Recovery RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
MAX3676EHJ+T 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 622Mbps 3.3V Clock Recovery RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
MAX3676EHJ-T 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 622Mbps 3.3V Clock Recovery RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
MAX3677CTJ+ 制造商:Microsemi Corporation 功能描述:+3.3V, LOW-JITTER CLOCK GEN W/MULT OUT - Trays 制造商:Microsemi Corporation 功能描述:Microsemi MAX3677CTJ+ Clocks - Timers 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC CLOCK GENERATOR PROGR 32TQFN 制造商:Microsemi Corporation 功能描述:IC CLOCK GENERATOR PROGR 32TQFN
MAX3677CTJ+T 制造商:Microsemi Corporation 功能描述:+3.3V, LOW-JITTER CLOCK GEN W/MULT OUT - Tape and Reel