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參數資料
| 型號： | MAX3640 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 3.3V.622Mbps LVDS.Dual 4:2 Crosspoint Switch |
| 中文描述： | 3.3V、622Mbps LVDS、雙路4:2交叉點開關 |
| 文件頁數： | 5/12頁 |
| 文件大?。?/td> | 327K |
| 代理商： | MAX3640 |
M
3.3V, 622Mbps LVDS,
Dual 4:2 Crosspoint Switch
_______________________________________________________________________________________
5
Pin Description
PIN
NAME
FUNCTION
1, 12, 25, 36,
41
V
CC
Positive Supply Voltage
2, 11, 26, 35
GND
Supply Ground
3, 5, 45, 47
DIA3+, DIA4+, DIA1+,
DIA2+
Positive LVDS, Channel-A Data Input
4, 6, 46, 48
DIA3-, DIA4-, DIA1-,
DIA2-
Negative LVDS, Channel-A Data Input
7, 9, 13, 15
DIB1+, DIB2+, DIB3+,
DIB4+
Positive LVDS, Channel-B Data Input
8, 10, 14, 16
DIB1-, DIB2-, DIB3-,
DIB4-
Negative LVDS, Channel-B Data Input
17
–
20
SEL1
–
SEL4
Crosspoint Switch Select, TTL Input. (Table 1)
21, 23, 27, 29
DOB4-, DOB3-, DOB2-,
DOB1-
Negative LVDS, Channel-B Data Output
22, 24, 28, 30
DOB4+, DOB3+,
DOB2+, DOB1+
Positive LVDS, Channel-B Data Output
31, 33, 37, 39
DOA4-, DOA3-, DOA2-,
DOA1-
Negative LVDS, Channel-A Data Output
32, 34, 38, 40
DOA4+, DOA3+,
DOA2+, DOA1+
Positive LVDS, Channel-A Data Output
42
ENB
Channel-B Output Enable, TTL Input. ENB = high enables DOB1
DOB4.
ENB = low powers down DOB1
DOB4 and sets them to a high-impedance state.
Channel-A Output Enable, TTL Input. ENA = high enables DOA1
DOA4.
ENA = low powers down DOA1
DOA4 and sets them to a high-impedance state.
43
ENA
44
IN_SEL
Input Select Pin, TTL Input. Connect to logic high (or V
CC
) to select DIA1
DIA4.
Connect to logic low (or GND) to select DIB1
DIB4.
Detailed Description
Figure 2 shows the MAX3640
’
s architecture. It consists
of two data paths; each data path begins with four dif-
ferential input buffers. The IN_SEL pin selects whether
the A or B channels are passed to the 2x2 crosspoint
switch that follows. The SEL_ pins control the routing of
the crosspoint switch. Each crosspoint switch output
drives a pair of LVDS output drivers. This provides a
redundant set of outputs that can be used for fan-out
or test purposes. Each set of outputs, DOA_ and
DOB_, is enabled or disabled by the ENA and ENB
pins. See Table 1 for routing controls.
LVDS Inputs and Outputs
The MAX3640 features LVDS inputs and outputs for
interfacing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifica-
tion. This technology uses 500mV to 800mV differential
low-voltage swings to achieve fast transition times, low
power dissipation, and improved noise immunity.
For proper operation, the data outputs require 100
dif-
ferential termination between the inverting and nonin-
verting pins. Do not terminate these outputs to ground.
See Figure 1 for LVDS output voltage specifications.
The data inputs are internally terminated with 100
dif-
ferential and therefore do not require external termina-
tion.
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