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參數(shù)資料
| 型號： | MAX3558EVKIT |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Evaluation Kit for the MAX3558 |
| 中文描述： | MAX3558評估板 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大小： | 398K |
| 代理商： | MAX3558EVKIT |
M
Detailed Description
Programmable-Gain Amplifier
The PGA consists of the variable-gain amplifier (VGA)
and the digital-to-analog converter (DAC), which pro-
vide better than 56dB of output-level control in 0.5dB
steps. The PGA is implemented as a programmable
Gilbert-cell attenuator. The gain of the PGA is deter-
mined by a 7-bit word (D6
–
D0) programmed through
the serial data interface (Tables 1 and 2).
Specified performance is achieved when the input is
driven differentially. The device may be driven single
ended. To drive the device in this manner, one of the
input pins must be capacitively coupled to ground. Use
a capacitor value large enough to allow for a low-
impedance path to ground at the lowest frequency of
operation. For operation down to 5MHz, a 0.001μF
capacitor is recommended.
Output Amplifiers
The output amplifiers are Class A differential amplifiers,
capable of driving 61dBmV (QPSK) differentially. This
architecture provides superior even-order distortion
performance but requires that a transformer be used to
convert to a single-ended output. In transmit-disable
mode, the output amplifiers are powered down. A resis-
tor is placed across the output, so that the output
impedance remains matched when the amplifier is in
transmit-disable mode. Disabling the output devices
also results in low output noise.
To match the output impedance to a 75
load, the trans-
former must have a turns ratio of 1:1. The differential
amplifier is biased directly from the 3.3V supply using the
center tap of the output transformer. This provides a sig-
nificant benefit when switching between transmit mode
and transmit-disable mode. Stored energy due to bias
currents cancels within the transformer and prevents
switching transients from reaching the load.
Serial Interface
The serial interface has an active-low enable (
CS
) to
bracket the data, with data clocked in MSB first on the
rising edge of SCLK. Data is stored in the storage latch
on the rising edge of
CS
. The serial interface controls
the state of the PGA and the output amplifiers. Tables 1
and 2 show the register format. Serial-interface timing is
shown in Figure 1.
Upstream CATV Amplifier
8
_______________________________________________________________________________________
Functional Diagram
MAX3503
GND
SDA SCLK
OUT-
OUT+
IN+
IN-
V
CC
TXEN
SHDN
CEXT
BIAS
CONTROL
HIGH
POWER
LOW
NOISE
D/A CONVERTER
SERIAL DATA INTERFACE
CS
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