參數(shù)資料
型號(hào): MAX3362AKA
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 通用總線功能
英文描述: Quad LVDS Transmitter 16-TSSOP -40 to 85
中文描述: LINE TRANSCEIVER, PDSO8
封裝: SOT-23, 8 PIN
文件頁(yè)數(shù): 7/14頁(yè)
文件大?。?/td> 315K
代理商: MAX3362AKA
M
3.3V, High-Speed, RS-485/RS-422 Transceiver in
SOT Package
_______________________________________________________________________________________
7
Pin Description
PIN
NAME
DESCRIPTION
1
RO
Receiver Output. RO is high if the receiver input differential (A-B)
200mV and the receiver is enabled
(
RE
is low). RO is low if the receiver input differential (A-B)
-200mV and the receiver is enabled.
2
RE
Receiver Output Enable. Driving
RE
low enables RO. RO is high impedance when
RE
is high. Drive
RE
high and DE low (disable both receiver and driver outputs) to enter low-power shutdown mode.
3
DE
Driver Output Enable. Driving DE high enables driver outputs. These outputs are high impedance
when DE is low. Drive
RE
high and DE low (disable both receiver and driver outputs) to enter low-
power shutdown mode.
4
DI
D ver Inp ut. D vi ng D l ow for ces the noni nver i ng outp ut l ow and i nver i ng outp ut hi g h, w hen the d ver i s
enab ed ( D E i s hi g h) D vi ng D hi g h for ces the noni nver i ng outp ut hi g h and i nver i ng outp ut l ow
5
6
7
8
GND
A
B
V
CC
Ground
Noninverting Receiver Input and Noninverting Driver Output
Inverting Receiver Input and Inverting Driver Output
Supply Voltage. V
CC
= 3.3V ±5%. Bypass V
CC
to GND with a 0.1μF capacitor.
OUT
V
CC
R
L
C
L
D
C
L
= 50pF
R
L
= 54
Figure 2. Driver Timing Test Circuit
0
V
CC
/2
V
CC
DI
B
A
t
PDLH
(A+B)/2
A - B
10%
90%
t
PDHL
t
ri
t
fi
t
ri
= 5ns
t
fi
= 5ns
t
DF
t
DR
Figure 3. Driver Propagation Delay
V
OD
V
CC
R
L
/2
R
L
/2
V
OC
D
Figure 1. Driver DC Test Load
IN
OUT
t
PDSL
, t
PDZL
t
PDLZ
0.25V
V
OL
0
V
CC
/2
V
OM
= (V
OL
+ V
CC
) /2
V
CC
V
CC
V
CC
R
L
= 500
C
L
= 50pF
GENERATOR
50
0 or 3V
OUT
S1
D
Figure 4. Driver Enable and Disable Times (t
PDSL
, t
PDZL
, t
PDLS
,
t
PDLZ
)
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