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參數(shù)資料
| 型號： | MAX3349EAETE |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | USB 2.0 Full-Speed Transceiver with UART Multiplexing Mode |
| 中文描述： | LINE TRANSCEIVER, QCC16 |
| 封裝： | 4 X 4 MM, 0.80 MM HEIGHT, MO-220WGGC, TQFN-16 |
| 文件頁數(shù)： | 10/17頁 |
| 文件大小： | 397K |
| 代理商： | MAX3349EAETE |
M
USB 2.0 Full-Speed Transceiver with UART
Multiplexing Mode
10
______________________________________________________________________________________
GND with a 0.1μF ceramic capacitor as close to the
device as possible. There are high-impedance resistors
~2M
to ground on D+ and D- to prevent floating
nodes when in UART mode and nothing is connected.
Operating Modes
The MAX3349EA operates in either USB mode or
UART mode, depending on the presence or absence
of V
BUS
. Bus detect output BD is logic-high when a
voltage higher than V
TH-VBUS
is applied to V
BUS
, and
logic-low otherwise. The MAX3349EA operates in USB
mode when BD is logic-high, and UART mode when
BD is logic-low.
USB Mode
In USB mode, the MAX3349EA implements a full-speed
(12Mbps) USB interface on D+ and D-, with enumerate
and suspend functions. A differential USB receiver pre-
sents the USB state as a logic-level output RCV (Table
3a). VP/VM are outputs of single-ended USB receivers
when
OE
is logic-high, allowing detection of single-
ended 0 (SE0) events. When
OE
is logic-low, VP and
VM serve as inputs to the USB transmitter. Drive sus-
pend input SUS logic-high to force the MAX3349EA into
a low-power operating mode and disable the differen-
tial USB receiver (Table 3b).
UART Mode
The MAX3349EA operates in UART mode when BD is
logic-low (V
BUS
not present). The Rx signal is the out-
put of a single-ended receiver on D+, and the Tx input
is driven out on D-. Signaling voltage thresholds for D+
and D- are determined by V
UART
, an externally applied
voltage between +2.7V and +3.3V.
Power-Supply Configurations
V
L
Logic Supply
In both USB and UART modes, the control interface is
powered from V
L
. The MAX3349EA operates with logic-
side voltage (V
L
) as low as +1.4V, providing level shift-
ing for lower voltage ASICs and microcontrollers.
Timing Diagrams (continued)
I
P
100%
90%
36.8%
t
RL
TIME
t
DL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Ir
10%
0
0
AMPERES
Figure 10. Human Body Model Current Waveform
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
150pF
R
C
50M
to 100M
R
D
330
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 11. IEC61000-4-2 ESD Contact Discharge Test Model
t
R
= 0.7ns to 1ns
30ns
60ns
t
100%
90%
10%
I
P
I
Figure 12. IEC 61000-4-2 Contact Discharge Model Current
Waveform
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