參數(shù)資料
型號: MAX3345EEUE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 通用總線功能
英文描述: 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors
中文描述: LINE TRANSCEIVER, PDSO16
封裝: 4.40 MM, MO-153AB, TSSOP-16
文件頁數(shù): 3/15頁
文件大小: 406K
代理商: MAX3345EEUE
M
±15kV ESD-Protected USB Transceivers
in UCSP with USB Detect
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 4V to 5.5V bypassed with 1μF to GND, GND = 0, V
L
= 1.65V to 3.6V, ENUM = V
L
, T
A
= T
MIN
to T
MAX
, unless otherwise
noted. Typical values are at V
CC
= 5V, V
L
= 2.5V, T
A
= +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Leakag e C ur ent
S U SP MOD E E N UM
OE
, VM O, V P O = 0 or
V
L
±1
μA
USB-SIDE I/O
Output-Voltage Low
Output-Voltage High
V
OL
V
OH
R
L
= 1.5k
from D+ or D- to 3.6V
R
L
= 15k
from D+ and D- to GND
Three-state driver, ENUM = 0, V
D_
= 0 or
+3.6V
0.3
3.6
V
V
2.8
Input Impedance
Z
IN
1
M
S ng e- E nd ed Inp ut- V ol ag e H g h
S ng e- E nd ed Inp ut- V ol ag e Low
V
IH
V
IL
2.0
V
V
0.8
Receiver Single-Ended
Hysteresis
V
HYS
200
mV
Differential Input Sensitivity
V
DIFF
200
mV
Input Common-Mode Voltage
Range
V
CM
0.8
2.5
V
Driver Output Impedance
Internal Pullup Resistor
R
OUT
R
PU
V
USBLH1
V
USBHL1
V
USBLH2
V
USBHL2
V
USBHYS
4.6
1.410
16.0
1.540
4.0
k
1.500
MAX3344E
MAX3344E
MAX3345E
MAX3345E
MAX3344E
3.6
2.8
USB_DET Threshold
1
V
USB_DET Hysteresis
LINEAR REGULATOR
External Capacitor
ESD PROTECTION (V
CC
, D+, D-)
Human Body Model
IE C 1000- 4- 2 Ai Gap D schar g e
IE C 1000- 4- 2 C ontact D schar g e
25
mV
C
OUT
Compensation of linear regulator
1
μF
±
15
±
10
±8
kV
kV
kV
TIMING CHARACTERISTICS
(V
CC
= 4V to 5.5V, GND = 0, V
L
= 1.65V to 3.6V, ENUM = V
L
, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at
V
CC
= 5V, V
L
= 2.5V, T
A
= +25°C.) (Figures 2–6) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TRANSMITTER
OE
to Transmit Delay Enable Time
t
PZD
Figures 2 and 6c
20
ns
OE
to Driver Three-State Delay
Driver Disable Time
t
PDZ
Figures 2 and 6c
20
ns
t
PLH1(drv)
t
PHL1(drv)
t
PLH0(drv)
t
PHL0(drv)
MODE = high, Figures 4 and 6b
MODE = high, Figures 4 and 6b
MODE = low, Figures 3 and 6c
MODE = low, Figures 3 and 6c
10
10
11
11
18
18
20
20
VPO/VMO to D+/D- Propagation
Delay
ns
VPO/VMO D+/D- Propagation
Delay
ns
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