參數(shù)資料
型號: MAX3320TEAP
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 通用總線功能
英文描述: Transceiver
中文描述: LINE TRANSCEIVER, PDSO20
封裝: 0.200 INCH, 0.65 MM PITCH, SSOP-20
文件頁數(shù): 7/17頁
文件大小: 389K
代理商: MAX3320TEAP
M
±15kV ESD-Protected USB Transceiver
in UCSP
_______________________________________________________________________________________
7
Detailed Description
The MAX3346E is a bidirectional transceiver that con-
verts single-ended or differential logic-level signals to
differential USB signals, and converts differential USB
signals to single-ended or differential logic-level sig-
nals. The MAX3346E includes an internal 1.5k
pullup
resistor that can be connected to either D+ or D- for
full-speed or low-speed operation (see the
Functional
Diagram
). The MAX3346E can be energized without
concern about power-supply sequencing. Additionally,
the USB I/O, D+ and D-, are ESD protected to ±15kV.
The MAX3346E can get its USB-side power, V
CC
,
directly from the USB connection, and can operate with
system-side power, V
L
, down to 1.65V and still meet the
USB physical layer specifications. The MAX3346E sup-
ports both full-speed (12Mbps) and low-speed
(1.5Mbps), USB specification 1.1 operation.
The MAX3346E has an enumerate feature that works
when power is on. Driving ENUM low disconnects the
internal 1.5k
pullup resistor from both D+ and D-,
reenumerating the USB. This is useful if changes in com-
munication protocol are required while power is applied,
and while the USB cable is connected.
PIN
TSSOP
UCSP
NAME
INPUT/
OUTPUT
FUNCTION
7
B2
SUSP
Input
Suspend Input. Drive SUSP low for normal operation. Force SUSP high for low-
power state. In low-power state RCV is low, D+/D- are high impedance if
OE
is
floating, and VP/VM are active outputs.
8
A2
SPEED
Input
USB Transmission Speed Select Input. If SPEED is forced high, full speed
(12Mbps) is selected and the internal 1.5k
pullup resistor is connected to D+.
If SPEED is forced low, low speed (1.5Mbps) is selected and the internal 1.5k
pullup resistor is connected to D-.
9
A3
VCC
Power
USB-Side Power-Supply Input. Connect V
CC
to the incoming USB power supply.
Bypass V
CC
to GND with a 1μF ceramic capacitor.
Ground
10
A4
GND
Power
11
B4
D-
Input/
Output
USB Differential Data Input/Output. Connect to the USB’s D- signal through a
24.3
±
1% resistor.
12
C4
D+
Input/
Output
USB Differential Data Input/Output. Connect to the USB’s D+ signal through a
24.3
±
1% resistor.
13
D4
VTRM
Power
Regulated Output Voltage. 3.3V output derived from the V
CC
input. Bypass
VTRM to GND with a 1μF (or more) low-ESR capacitor, such as ceramic or
plastic film types.
14
D3
VL
Power
System-Side Power-Supply Input. Connect to the system’s logic-level power
supply, 1.65V to 3.6V. Bypass to GND with a 0.1μF capacitor.
B3, C3
Not populated. The solder sphere is omitted from these locations (see the
Package Information
).
Pin Description (continued)
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