M
USB On-the-Go Transceiver and Charge Pump
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25
BIT NUMBER
SYMBOL
CONTENTS
VALUE AT
POWER-UP
0
vbus_vld
S et to 0 to d sab e the vb us_vld i nter up for a hig h- o- ow transiti on. S et to 1 to
enab e the vb us_vld i nter up for a hig h- o- ow transiti on. S ee Tab es 10 and 11.
0
1
sess_vld
S et to 0 to d sab e the sess_vld i nter up for a hig h- o- ow transiti on. S et to 1 to
enab e the sess_vld i nter up for a hig h- o- ow transiti on. S ee Tab es 10 and 11.
0
2
dp_hi
S et to 0 to d sab e the d p _hi interr up for a hi g h-to- ow tr ansi i on. Set to 1 to
enab e the d p _hi interr up for a hi g h-to- ow tr ansi i on. See Tab es 10 and 11.
0
3
id_gnd
S et to 0 to d sab e the i d _g nd i nter upt for a hi g h- o-l ow tr ansi ion. S et to 1 to
enab e the i d _g nd i nter upt for a hi g h- o-l ow tr ansi ion. S ee Tab es 10 and 11.
0
4
dm_hi
S et to 0 to d sab e the d m _hi interr up for a hi g h-to- ow tr ansi i on. Set to 1 to
enab e the d m _hi interr up for a hi g h-to- ow tr ansi i on. See Tab es 10 and 11.
0
5
id_float
S et to 0 to d sab e the i d _fl oat i nter up for a hig h- o- ow transiti on. S et to 1 to
enab e the i d _fl oat i nter up for a hig h- o- ow transiti on. S ee Tab es 10 and 11.
0
6
bdis_acon
S et to 0 to d sab e the b d s_acon interr up for a hi g h-to- ow tr ansi i on. Set to 1 to
enab e the b d s_acon interr up for a hi g h-to- ow tr ansi i on. See Tab es 10 and 11.
0
7
cr_int_sess_end
S et to 0 to d sab e the cr _i nt_sess_end i nter up for a hi g h- o- ow tr ansi i on.
S et to 1 to enab e the cr _i nt_sess_end i nter up for a hi g h- o- ow tr ansi i on.
S ee Tab es 10 and 11.
0
Table 12. Interrupt-Enable Low Register (Write to Address 0Ch to Set, Write to Address
0Dh to Clear)
BIT NUMBER
SYMBOL
CONTENTS
VALUE AT
POWER-UP
0
vbus_vld
S et to 0 to d sab e the vb us_vld i nter up for a l ow o- hi gh transiti on. S et to 1 to
enab e the vb us_vld i nter up for a l ow o- hi gh transiti on. S ee Tab es 10 and 11.
0
1
sess_vld
S et to 0 to d sab e the sess_vld i nter up for a l ow o- hi gh transiti on. S et to 1 to
enab e the sess_vld i nter up for a l ow o- hi gh transiti on. S ee Tab es 10 and 11.
0
2
dp_hi
S et to 0 to d sab e the d p _hi i nter up for a l ow o- hi g h tr ansi i on. S et to 1 to
enab e the d p _hi i nter up for a l ow o- hi g h tr ansi i on. S ee Tab es 10 and 11.
0
3
id_gnd
S et to 0 to d sab e the i d _g nd i nter up for a l ow o- hi g h tr ansi i on. S et to 1 to
enab e the i d _g nd i nter up for a l ow o- hi g h tr ansi i on. S ee Tab es 10 and 11.
0
4
dm_hi
S et to 0 to d sab e the d m _hi i nter up for a l ow o- hi g h tr ansi i on. S et to 1 to
enab e the d m _hi i nter up for a l ow o- hi g h tr ansi i on. S ee Tab es 10 and 11.
0
5
id_float
S et to 0 to d sab e the i d _fl oat i nter up for a l ow o- hi g h tr ansi i on. S et to 1 to
enab e the i d _fl oat i nter up for a l ow o- hi g h tr ansi i on. S ee Tab es 10 and 11.
0
6
bdis_acon
S et to 0 to d sab e the b d s_acon interr up for a low o- hig h tr ansi i on. Set to 1 to
enab e the b d s_acon interr up for a low o- hig h tr ansi i on. See Tab es 10 and 11.
0
7
cr_int_sess_end
S et to 0 to d sab e the cr _i nt_sess_end i nter up for a l ow o- hi g h tr ansi i on.
S et to 1 to enab e the cr _i nt_sess_end i nter up for a l ow o- hi g h tr ansi i on.
S ee Tab es 10 and 11.
0
Table 13. Interrupt-Enable High Register (Write to Address 0Eh to Set, Write to Address
0Fh to Clear)