參數(shù)資料
型號: MAX3272EGP
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 數(shù)字傳輸電路
英文描述: +3.3V, 2.5Gbps Low-Power Limiting Amplifier
中文描述: ATM/SONET/SDH SUPPORT CIRCUIT, QCC20
封裝: 4 X 4 MM, 0.90 MM HEIGHT, MO-220, QFN-20
文件頁數(shù): 6/14頁
文件大小: 625K
代理商: MAX3272EGP
M
Detailed Description
Figure 2 is a functional diagram of the MAX3272/
MAX3272A, comprising a CML input buffer, power
detector and loss-of- signal indicators, gain stage, offset-
correction loop, and CML output buffer.
CML Input Buffer
The input buffer (Figure 3) provides 100
input imped-
ance between IN+ and IN-. DC-coupling the inputs is
not recommended; this prevents the DC offset-correc-
tion circuitry from functioning properly.
Power Detect and
Loss-of-Signal Indicator
The MAX3272/MAX3272A are equipped with loss-of-sig-
nal (LOS) circuitry that indicates when the input signal is
below a programmable threshold, set by resistor R
TH
at
the TH pin (see the
Typical Operating Characteristics
for
appropriate resistor selection). An averaging peak-
power detector compares the input signal amplitude
with this threshold and feeds the signal-detect informa-
tion to the LOS outputs, which are internally terminated
to 8k
(Figure 4).
+3.3V, 2.5Gbps Low-Power
Limiting Amplifiers
6
_______________________________________________________________________________________
CML SUPPLY CURRENT (I
CC
)
V
CC
I
CC
I
OUT
50
R
TH
50
CONTROL
SQUELCH
OPEN
LEVEL
OPEN
MAX3272/
MAX3272A
Figure 1. Power-Supply Current Measurement
MAX3272/
MAX3272A
TTL
TTL
CONTROL
POWER
DETECTOR
IN+
IN-
100
POWER DETECTOR AND
LOS INDICATOR
CML
INPUT
BUFFER
CML
OUTPUT
BUFFER
OFFSET
CORRECTION
0.1
μ
F
LOWPASS
FILTER
LOS
SQUELCH
OUT+
OUT-
LEVEL
OUTPOL
LOS
CAZ1
CAZ2
TH
CLOS
Figure 2. Functional Diagram
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