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參數(shù)資料
| 型號： | MAX3227IDBG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RS232 3V5.5V 15KVESD 16-SSOP |
| 標準包裝： | 80 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | RS232 |
| 電源電壓： | 3 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 管件 |
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PARAMETER MEASUREMENT INFORMATION
50
TEST CIRCUIT
VOLTAGE WAVEFORMS
3 V
0 V
3 V
Output
Input
VOL
VOH
tTLH
Generator
(see Note B)
RL
3 V
FORCEOFF
RS-232
Output
tTHL
CL
(see Note A)
SR(tr) +
6 V
t
THL or tTLH
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 , 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
50
TEST CIRCUIT
VOLTAGE WAVEFORMS
0 V
3 V
Output
Input
VOL
VOH
tPLH
Generator
(see Note B)
RL
3 V
FORCEOFF
RS-232
Output
tPHL
CL
(see Note A)
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 , 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
50%
1.5 V
TEST CIRCUIT
VOLTAGE WAVEFORMS
50
3 V
Output
Input
VOL
VOH
tPHL
Generator
(see Note B)
tPLH
Output
CL
(see Note A)
3 V or 0 V
FORCEON
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: ZO = 50 , 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
3 V
FORCEOFF
1.5 V
50%
3-V TO 5.5-V SINGLE-CHANNEL RS-232 LINE DRIVER/RECEIVER
WITH
±15-kV ESD PROTECTION
SLLS673A – AUGUST 2005 – REVISED FEBRUARY 2006
Figure 1. Driver Slew Rate
Figure 2. Driver Pulse Skew
Figure 3. Receiver Propagation Delay Times
8
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