參數(shù)資料
型號(hào): MAX3173CAI+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 4/15頁(yè)
文件大小: 0K
描述: IC TXRX CLK MULTIPROT 28-SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 46
類型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 3/3
規(guī)程: RS232
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 28-SSOP
包裝: 管件
MAX3171/MAX3173
+3.3V Multiprotocol 3Tx/3Rx
Software-Selectable Control Transceivers
12
______________________________________________________________________________________
Safe). To aid in rejecting system noise, the
MAX3171/MAX3173 V.10 receiver has 15mV (typ) hys-
teresis. Switch S3 in Figure 11 is open in V.10 mode to
disable the 5k
V.28 termination at the receiver input.
Switch S4 is closed, and switch S5 is open to internally
ground the receiver B input.
V.28 Interface
The V.28 interface is an unbalanced single-ended inter-
face (Figure 12). The V.28 generator provides ±5V
(min) across the load impedance between A’ and C’.
The V.28 standard specifies input trip points at ±3V.
The MAX3171/MAX3173 V.28 mode receiver has a
threshold between +0.8V and +2.0V to ensure that the
receiver has proper fail-safe operation (see Fail-Safe). To
aid in rejecting system noise, the MAX3171/MAX3173
V.28 receiver has a 500mV (typ) hysteresis. Switch S3 in
Figure 12 is closed in V.28 mode to enable the 5k
V.28
termination at the receiver input.
Receiver Glitch Rejection
To facilitate operation in an unterminated or otherwise
noisy system, the MAX3171 features 10s of receiver
input glitch rejection in V.10, V.11, and V.28 modes.
The glitch rejection circuitry blocks the reception of
high-frequency noise (tB < 5s) while receiving a low-
frequency signal (tB > 15s), allowing glitch-free opera-
tion in unterminated systems at up to 64kbps. The
MAX3173 does not have this feature and can be oper-
ated at data rates up to 240kbps if properly terminated.
DTE vs. DCE Operation
Figure 13 shows a DCE or DTE controller-selectable
interface. The DCE/DTE input switches the port’s mode
of operation. A logic high selects DCE, which enables
Figure 13. Multiprotocol DCE/DTE Port
D1
D2
D3
R1
R2
R3
MAX3170
RXD(DTE)
TXD(DCE)
RXC(DTE)
SCTE(DCE)
LL(DTE)
LL(DCE)
TXD(DTE)
RXD(DCE)
TXC(DTE)
TXC(DCE)
SCTE(DTE)
RXC(DCE)
M1
M2
M0
DCE/DTE
M1
M2
M0
DCE/DTE
D1
R4
D4
D2
D3
R1
R2
R3
MAX3171
MAX3173
M1
M2
M0
DCE/DTE
CTS(DTE)
RTS(DCE)
DSR(DTE)
DTR(DCE)
RTS(DTE)
CTS(DCE)
DTR(DTE)
DSR(DCE)
DCD(DTE)
DCD(DCE)
M2
M1
M0
DCE/DTE
CTS
B
CTS
A
DSR
B
DSR
A
DCD
B
DCD
A
DTR
B
DTR
A
RTS
B
RTS
A
SHIELD
SG
LL
A
RXD
B
RXD
A
RXC
B
RXC
A
TXC
B
TXC
A
SCTE
B
SCTE
A
TXD
B
TXD
A
DB-25 CONNECTOR
DTE
DCE
RTS
B
RTS
A
DTR
B
DTR
A
DCD
B
DCD
A
DSR
B
DSR
A
CTS
B
CTS
A
LL
A
TXD
B
TXD
A
SCTE
B
SCTE
A
TXC
B
TXC
A
RXC
B
RXC
A
RXD
B
RXD
A
13 5
10 8
22 6
23 20 19 4
1
7
18
16 3
9 17
12 15 11 24 14 2
MAX3172
MAX3174
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