參數(shù)資料
型號(hào)： MAX3172
廠商： Maxim Integrated Products, Inc.
英文描述： Quad LVDS Receiver 16-TSSOP -40 to 85
中文描述： +3.3V、多協(xié)議、軟件可選的電纜端接器及收發(fā)器
文件頁(yè)數(shù)： 12/19頁(yè)
文件大?。?/td> 276K
代理商： MAX3172
M
+3.3V Multiprotocol Software-Selectable
Cable Terminators and Transceivers
12
______________________________________________________________________________________
with a minimum of a 100
resistor (Figure 6). This resis-
tor, although not required, prevents reflections from
corrupting transmitted data.
In Figure 7, the MAX3172/MAX3174 are used to termi-
nate the V.11 receiver. Internal to the MAX3172/
MAX3174, S1 is closed and S2 is open to present a
104
typical differential resistance and high-Z com-
mon-mode impedance. S3 opens to disable the
MAX3170
’
s internal V.28 termination.
The V.11 specification allows for signals with common-
mode variations of ±7V with differential signal ampli-
tudes from 2V to 6V. Also, data rates may be as high as
10Mbps. The MAX3172/MAX3174 maintain steady ter-
mination impedance between 100
and 110
over
these conditions.
V.35 Termination
Figure 8 shows a standard V.35 interface. The genera-
tor and the load must both present a 100
±10
differ-
ential impedance and a 150
±15
common-mode
impedance (as shown by the resistive T-networks in
Figure 8). The V.35 driver generates a current output
(typically ±11mA) that develops an output voltage
between 440mV and 660mV across the load termina-
tion networks.
R6
10k
R8
5k
R3
127
R2
52
R1
52
A
′
B
′
C
′
A
B
GND
R5
30k
R7
10k
R4
30k
MAX3172
MAX3174
MAX3170
S3
S2
S1
RECEIVER
50
50
125
50
50
125
A
′
B
′
C
′
A
B
C
GENERATOR
BALANCED
INTERCONNECTING
CABLE
CABLE
TERMINATION
RECEIVER
LOAD
Figure 8. Typical V.35 Interface
Figure 7. V.11 Termination and Internal Resistance Networks
相關(guān)PDF資料
PDF描述
MAX3172CAI Quad LVDS Receiver 16-TSSOP -40 to 85
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MAX3185CAP 2.5-V/3.3-V Oscillator Gain Stage/Buffer with Enable 8-WSON -40 to 85
MAX3185EAP 2.5-V/3.3-V Oscillator Gain Stage/Buffer with Enable 8-WSON -40 to 85
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