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參數(shù)資料
| 型號(hào)： | MAX3140EEI+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 15/36頁(yè) |
| 文件大小： | 0K |
| 描述： | IC UART W/RS485 28-QSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 特點(diǎn)： | 收發(fā)器 |
| FIFO's： | 8 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-QSOP |
| 供應(yīng)商設(shè)備封裝： | 28-QSOP |
| 包裝： | 帶卷 (TR) |
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MAX3140
SPI/MICROWIRE-Compatible UART with Integrated
True Fail-Safe RS-485/RS-422 Transceivers
22
______________________________________________________________________________________
Baud-Rate Generator
The baud-rate generator determines the rate at which
the transmitter and receiver operate. Bits B3–B0 in the
WRITE CONFIGURATION register determine the baud-
rate divisor (BRD), which divides the X1 oscillator
frequency. The on-board oscillator operates with either
a 1.8432MHz or a 3.6864MHz crystal, or is driven at X1
with a 45% to 55% duty-cycle square wave. Table 6
shows baud-rate divisors for given input codes, as well
as the baud rate for 1.8432MHz and 3.6864MHz crys-
tals. The generator’s clock is 16 times the baud rate.
Interrupt Sources and Masks
Using the READ DATA or WRITE DATA register clears
the interrupt IRQ, assuming the conditions that initiated
the interrupt no longer exist. Table 7 gives the details
for each interrupt source. Figure 15 shows the function-
al diagram for the interrupt sources and mask blocks.
Two examples of setting up an IRQ for the MAX3140
are shown below.
Example 1: Setting up only the transmit buffer-empty
interrupt.
Send the 16-bit word below into DIN of the MAX3140
using the WRITE CONFIGURATION register. This 16-bit
word configures the MAX3140 for 9600bps, 8-bit words,
no parity, and one stop bit with a 1.8432MHz crystal.
binary 1100100000001010
HEX
C80A
Notes:
bit 15, 14: DIN
0, 0 = Read Data
bit 13–0: DIN
Zeros
bit 15: DOUT
R = 1, Data is available to be read from the receive register or
FIFO.
R = 0, Receive register and FIFO are empty.
bit 14: DOUT
T = 1, Transmit buffer is empty.
T = 0, Transmit buffer is full.
bit 13–11: DOUT
Zeros
bit 10: DOUT
RA/FE = Receive-activity (UART shutdown)/Framing-error
(normal operation) bit
bit 9: DOUT
CTS = CTS input state. If CTS = 0, then CTS = 1 and vice versa.
bit 8: DOUT
Pr = Received parity bit. This is only valid if PE = 1.
bit 7–0: DOUT
D7t–D0t = Received Data bits. D7r = 0 for L = 1.
Table 5. READ DATA Register Bit Assignment (D15, D14 = 0, 0)
14
0
T
6
0
D6r
7
0
D7r
15
2
DIN
0
DOUT
R
D2r
BIT
3
0
D3r
0
0
D0r
1
0
D1r
4
0
D4r
5
0
D5r
10
0
RA/FE
11
0
8
0
Pr
9
0
CTS
12
0
13
0
Table 6. Baud-Rate Selection Table*
115.2k
230.4k**
BAUD
RATE
(fOSC =
3.6864MHz)
BAUD
B3
B2 B1 B0
2
00
0
1
0
0**
DIVISION
RATIO
57.6k
115.2k**
BAUD
RATE
(fOSC =
1.8432MHz)
28.8k
57.6k
8
00
1
4
00
1
0
14.4k
28.8k
7200
14.4k
1800
3600
128
01
1
64
01
1
0
900
1800
32
01
0
1
16
01
0
3600
7200
38.4k
76.8k
9600
19.2k
24
10
1
12
10
1
0
4800
9600
2400
4800
600
1200
384
11
1
192
11
1
0
300
600
96
11
0
1
48
11
0
1200
2400
6
10
0
1
3
10
0
19.2k
38.4k
*Standard baud rates shown in bold
**Default baud rate
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