參數(shù)資料
型號： MAX3111EENI
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 微控制器/微處理器
英文描述： 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors
中文描述： 1 CHANNEL(S), SERIAL COMM CONTROLLER, PDIP28
封裝： 0.300 INCH, PLASTIC, DIP-28
文件頁數(shù)： 14/32頁
文件大?。?/td> 413K
代理商： MAX3111EENI
M
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
14
______________________________________________________________________________________
Notice to High-Level Programmers:
The UART follows
the SPI convention of providing a bidirectional data path
for writes and reads. Whenever the data is written, data
is also read back. This speeds operation over the SPI
bus, and the UART needs this speed advantage when
operating at high baud rates. In most high-level lan-
guages, such as C, there are commands for writing and
reading stream I/O devices such as the console or serial
port. In C specifically, there is a “PUTCHAR” command
that transmits a character and a “GETCHAR” command
that receives a character. If programmers were to write
direct write and read commands in C with no underlying
driver code, they would notice that a PUTCHAR com-
mand is really a PUTGETCHAR command. These C
commands assume some form of BIOS-level support for
these commands. The proper way to implement these
commands is to write driver code, usually in the form of
an assembly-language interrupt-service routine and a
callable routine used by high-level routines. This driver
handles the interrupts and manages the receive and
transmit buffers for the MAX3110E/MAX3111E. When a
PUTCHAR executes, this driver is called and it safely
buffers any characters received when the current
character is transmitted. When a GETCHAR executes, it
checks its own receive buffer before getting data from
the UART. See the C-language Outline of a MAX3110E/
MAX3111E Software Driver n Listing 1, which appears at
the end of this data sheet.
Listing 1 is a C-language outline of an interrupt-driven
software driver that interfaces to a MAX3110E/
MAX3111E, providing an intermediate layer between
the bit-manipulation subroutine and the familiar
PUTCHAR/GETCHAR subroutines.
The user must supply code for managing the transmit
and receive queues as well as the low-level hardware
interface itself. The interrupt control hardware must be
initialized before this driver is called.
Table 1. Bit Descriptions (continued)
POR
STATE
DESCRIPTION
BIT
TYPE
BIT
NAME
0
SHDNi
write
Software-Shutdown Bit. Enter software shutdown with a Write Configuration where SHDNi = 1.
Software shutdown takes effect after
CS
goes high, and causes the oscillator to stop as soon
as the transmitter becomes idle. Software shutdown also clears R, T, RA/FE, D0r–D7r,
D0t–D7t, Pr, Pt, and all data in the receive FIFO. RTS and CTS can be read and updated
while in shutdown. Exit software shutdown with a Write Configuration where SHDNi = 0. The
oscillator restarts typically within 50ms of
CS
going high. RTS and CTS are unaffected. Refer
to the Pin Description or hardware shutdown (
SHDN
input).
Shutdown Read-Back Bit. The Read Configuration register outputs SHDNo = 1 when the
UART is in shutdown. Note that this bit is not sent until the current byte in the transmitter is
sent (T = 1). This tells the processor when it may shut down the RS-485/RS-422 driver. This bit
is also set immediately when the device is shut down through the
SHDN
pin.
Transmit-Stop Bit. One stop bit will be transmitted when ST = 0. Two stop bits will be transmit-
ted when ST = 1. The receiver only requires one stop bit.
Reads the value of the ST bit.
Transmit-Buffer-Empty Flag. T = 1 means that the transmit buffer is empty and ready to
accept another data word.
Transmit-Enable Bit. If
TE
= 1, then only the
RTS
pin is updated on
CS
’s rising edge. The con-
tents of
RTS
, Pt, and D0t–D7t transmit on
CS
’s rising edge when
TE
= 0.
0
SHDNo
read
0
RA/FE
read
Receiver-Activity/Framing-Error Bit. In shutdown mode, this is the RA bit. In normal operation,
this is the FE bit. In shutdown mode, a transition on RX sets RA = 1. In normal mode, a fram-
ing error sets FE = 1. A framing error occurs if a zero is received when the first stop bit is
expected. FE is set when a framing error occurs, and cleared upon receipt of the next proper-
ly framed character independent of the FIFO being enabled. When the device wakes up, it is
likely that a framing error will occur. This error is cleared with a Write Configuration. The FE bit
is not cleared on a Read Data operation. When an FE is encountered, the UART resets itself
to the state where it is looking for a start bit.
0
ST
write
0
ST
read
0
0
TM
TM
write
read
Mask for T Bit.
IRQ
is asserted if
TM
= 1 and T = 1 (Table 7).
Reads the value of the
TM
bit (Table 7).
1
T
read
0
TE
write
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX3111EENI+G36 功能描述:UART 接口集成電路 5V SPI/uWire Compatible RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
MAX3111EEVKIT+ 功能描述:UART 接口集成電路 Evaluation Kit for the MAX3111E RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
MAX3111EEWI 功能描述:UART 接口集成電路 RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
MAX3111EEWI+G36 功能描述:UART 接口集成電路 5V SPI/uWire Compatible RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
MAX3111EEWI+T 功能描述:UART 接口集成電路 RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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