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          參數(shù)資料
          型號: MAX3111
          廠商: Maxim Integrated Products, Inc.
          元件分類: RS-232
          英文描述: 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors
          中文描述: 5V的高速RS - 232收發(fā)器與0.1uF電容
          文件頁數(shù): 11/32頁
          文件大小: 413K
          代理商: MAX3111
          SPI/MICROWIRE-Compatible UART and ±15kV ESD-
          Protected RS-232 Transceivers with Internal Capacitors
          ______________________________________________________________________________________
          11
          M
          SPI Interface
          The MAX3110E/MAX3111E are compatible with SPI,
          QSPI (CPOL = 0, CPHA = 0), and MICROWIRE serial-
          interface standards (Figure 2). The MAX3110E/
          MAX3111E have a unique full-duplex-only architecture
          that expects a 16-bit word for DIN and simultaneously
          produces a 16-bit word for DOUT regardless of which
          read/write register is used. The DIN stream is moni-
          tored for its first two bits to tell the UART the type of
          data transfer being executed (see the Write
          Configuration Register, Read Configuration Register,
          Write Data Register and Read Data Register sections).
          DIN (MOSI) is latched on SCLK’s rising edge. DOUT
          (MISO) should be read into the μP on SCLK’s rising
          edge. The first bit (bit 15) of DOUT transitions on
          CS
          ’s
          falling edge, and bits 14–0 transition on SCLK’s falling
          edge. Figure 3 shows the detailed serial timing specifi-
          cations for the synchronous SPI port.
          Only 16-bit words are expected. If
          CS
          goes high in the
          middle of a transmission (any time before the 16th bit),
          the sequence is aborted (i.e., data does not get written
          to individual registers). Most operations, such as the
          clearing of internal registers, are executed only on
          CS
          ’s
          rising edge. Every time
          CS
          goes low, a new 16-bit
          stream is expected. An example of using the Write
          Configuration Register is shown in Figure 4.
          Table 1 describes the bits located in the Write Config-
          uration, Read Configuration, Write Data, and Read
          Data Registers. This table also describes whether the
          bit is a read or a write bit and the power-on reset state
          (POR) of the bits. Figure 5 shows an example of parity
          and word-length control.
          CS
          SCLK
          SCLK
          SCLK
          SCLK
          (CPOL = 0, CPHA = 0)
          (CPOL = 0, CPHA = 1)
          (CPOL = 1, CPHA = 0)
          (CPOL = 1, CPHA = 1)
          COMPATIBLE
          WITH MAX3110E/MAX3111E
          NOT COMPATIBLE
          WITH MAX3110E/MAX3111E
          DIN
          MSB
          13
          14
          12
          11
          10
          9
          8
          7
          6
          5
          4
          3
          2
          1
          LSB
          DOUT
          MSB
          13
          14
          12
          11
          10
          9
          8
          7
          6
          5
          4
          3
          2
          1
          LSB
          Figure 2. Compatible CPOL and CPHA Timing Modes
          CS
          SCLK
          DIN
          DOUT
          t
          CSO
          t
          CSS
          t
          CL
          t
          DS
          t
          DH
          t
          DV
          t
          CH
          t
          DO
          t
          TR
          t
          CSH
          t
          CS1
          Figure 3. Detailed Serial Timing Specifications for the Synchronous SPI Port
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          參數(shù)描述
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